Methods And Apparatus For Generating Clock Signals By Normalizing Duty Code To Period Code

Abstract

A clock signal generating method includes receiving a duty code that represents a duty of a clock signal, and a period code that represents a period of a clock signal, and normalizing the duty code to the period code to output a normalized duty code. The clock signal generating method further includes controlling a rising timing of a clock signal in response to the period code, and controlling a falling timing of the clock signal in response to the normalized duty code to generate a timing-controlled clock signal.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of Korean Patent Application No. 10-2013-0008895 filed in the Korean Intellectual Property Office on Jan. 25, 2013, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0003] Example embodiments relate to a clock signal generation technique, and more particularly, to a clock signal generation method capable of maintaining a constant duty ratio despite a frequency variation by normalizing a duty ratio code to a period code and a method capable of performing the same. A device for generating a clock signal. Background technique [0004] Frequency synthesizers are commonly used in digital systems. In electronic circuits, especially in synchronous digital systems, frequency synthesizers are used to generate clock signals. Frequency synthesizers usually take the form of phase-locked loop (PLL) circuits and delay-locked loop (DLL) circuits. A P...

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Problems solved by technology

PLLs include voltage controlled oscillators (VCOs); however, DLLs include delay lines and do not include VCOs

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