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Cell and macro placement on fin grid

A technology of grid lines and standard cells, applied in electrical components, special data processing applications, instruments, etc., can solve problems such as complex processes

Active Publication Date: 2014-08-27
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This leads to a more complex process for forming the fins

Method used

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  • Cell and macro placement on fin grid
  • Cell and macro placement on fin grid
  • Cell and macro placement on fin grid

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Embodiment Construction

[0031] In the following, the manufacture and use of various embodiments of the present invention are discussed in detail. However, it should be understood that the present invention provides many applicable concepts that can be implemented in various specific environments. The specific embodiments discussed merely illustrate specific ways of making and using the present invention, and are not intended to limit the scope of the present invention.

[0032] According to various exemplary embodiments, there are provided a semiconductor die, an integrated circuit formed therein, and a method of forming the semiconductor die. The intermediate stages of forming the die are shown. The variations of the embodiment are discussed. In the various views and illustrative embodiments, similar reference numerals are used to represent similar elements.

[0033] figure 1 The layout steps in integrated circuit design are shown. According to some embodiments, a computer 10 ( image 3 ) To perform...

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Abstract

A die includes at least one standard cell, which includes a first boundary and a second boundary opposite to the first boundary. The first boundary and the second boundary are parallel to a first direction. The at least one standard cell further includes a first plurality of FinFETs including first semiconductor fins parallel to the first direction. The die further includes at least one memory macro, which has a third boundary and a fourth boundary opposite to the third boundary. The third boundary and the fourth boundary are parallel to the first direction. The at least one memory macro includes a second plurality of FinFETs including second semiconductor fins parallel to the first direction. All semiconductor fins in the at least one standard cell and the at least one memory macro have pitches equal to integer times of a minimum pitch of the first and the second semiconductor fins.

Description

[0001] Cross reference of related applications [0002] The present invention claims the rights and interests of the following US patent application No. 61 / 770,224, which was provisionally filed on February 27, 2013, entitled "Cell and Macro Placement on Fin Grid", the entire content of which is incorporated herein by reference. . Technical field [0003] The present invention relates to the field of semiconductors, and more specifically, the present invention relates to a cell and macro arrangement on a fin grid. Background technique [0004] As integrated circuits become more and more scaled down and the requirements for integrated circuit speed become higher and higher, transistors are required to have increasingly larger drive currents and smaller and smaller sizes. In order to meet these conflicting requirements, fin field effect transistors (FinFETs) were developed. FinFETs have larger trench widths than flat transistors. The trench width is increased by forming a trench in...

Claims

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Application Information

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IPC IPC(8): H01L27/02G06F17/50
Inventor 杨国男林周坤高章瑞蔡逸群赵坚如王中兴
Owner TAIWAN SEMICON MFG CO LTD