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Method for Failure Analysis of Semiconductor Chips

A technology of failure analysis and analysis method, applied in semiconductor/solid-state device testing/measurement, electrical components, circuits, etc., can solve the problems of difficulty in sample failure analysis, inability to replace the sample analysis method and re-analysis, etc., to achieve the effect of improving reliability

Active Publication Date: 2017-03-29
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the existing technology, all the structures to be analyzed of the sample are analyzed in one analysis process, and it is impossible to re-analyze the sample replacement analysis method, especially in the case of a limited number of samples, for a comprehensive and accurate failure analysis of the sample. have greater difficulties

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  • Method for Failure Analysis of Semiconductor Chips
  • Method for Failure Analysis of Semiconductor Chips
  • Method for Failure Analysis of Semiconductor Chips

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Embodiment Construction

[0026] When analyzing semiconductor chips in the prior art, all the structures to be analyzed of the sample are analyzed in one analysis process, and it is impossible to re-analyze the sample replacement analysis method, especially when the number of samples is limited. Comprehensive and accurate failure analysis has great difficulty.

[0027] In order to solve the above problems, the present invention provides a method for semiconductor chip failure analysis, which is used to analyze several semiconductor structures on the semiconductor chip, including:

[0028] providing a semiconductor chip to be analyzed, wherein the semiconductor chip includes a plurality of semiconductor structures;

[0029] Failure analysis is performed on the plurality of semiconductor structures by using different analysis methods.

[0030] The technical solutions of the present invention will be described in detail below in conjunction with specific implementations. In order to better illustrate th...

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Abstract

The invention provides a method for semiconductor chip failure analysis. The method is used for analyzing a plurality of semiconductor structures on a semiconductor chip. The method comprises the steps of providing a to-be-analyzed semiconductor chip, wherein the semiconductor chip comprises the semiconductor structures; and utilizing different analyzing modes to respectively perform failure analysis on the semiconductor structures. According to the analysis method, failure analysis can be performed on different sandwich structures on the same semiconductor chip by adopting the different analyzing modes.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for failure analysis of a sandwich structure in a semiconductor chip. Background technique [0002] In the manufacturing process of integrated circuits, there are hundreds of millions of various semiconductor structures in the semiconductor substrate, among which there are many structures similar to sandwiches, such as the capacitor structure (Metal-Isolator-Metal, MIM), which is sandwiched between two metal layers. A thin insulating layer, and for example, the gate (Gate) is a silicon oxide layer sandwiched between a polysilicon layer and a silicon substrate. These two sandwich structures have an insulating layer or a silicon oxide layer in the middle, which is electrically isolated. effect. However, due to process problems or design problems, various defects will appear on the interlayer (insulating layer or silicon oxide layer) of the sandwich structure, espec...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66
CPCH01L22/12
Inventor 陈强
Owner SHANGHAI HUALI MICROELECTRONICS CORP