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EDA tools and methods for collision detection during multiple patterning lithography

A multi-patterning and patterning technology, applied in the field of semiconductor manufacturing, can solve problems such as triple patterning conflicts

Active Publication Date: 2017-07-21
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

For example, in the case of MPT (Triple Patterning Technology, TPT) using three photomasks for exposing a single layer, if without violating the minimum separation distance design rule for at least one of the three masks, There is no way to divide the circuit pattern of this layer between the three masks, and there is a triple patterning native conflict

Method used

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  • EDA tools and methods for collision detection during multiple patterning lithography
  • EDA tools and methods for collision detection during multiple patterning lithography
  • EDA tools and methods for collision detection during multiple patterning lithography

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Embodiment Construction

[0043] This description of the exemplary embodiments is intended to be read in conjunction with the accompanying drawings, which are considered a part of the entire written description. In the specification, expressions such as "lower", "upper", "horizontal", "vertical", "above", "below", "upward", "downward", "top" and " Relative terms of "bottom" and derivatives thereof (eg, "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation described or shown in the figure in question. These relative terms are for convenience of description and do not require that the device be configured or operated in a particular orientation.

[0044] Integrated circuits are fabricated by photolithography, which includes the formation of wires and shapes such as, but not limited to, copper lines in the interconnect layers of an IC, or diffusion regions in the active device layers of an IC. These lines and shapes are often referred to as patterns or polygons. ...

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PUM

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Abstract

A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of US Provisional Patent Application No. 61 / 781,098, filed March 14, 2013, the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention relates generally to semiconductor fabrication, and more particularly to multiple patterning of semiconductor substrates. Background technique [0004] In semiconductor manufacturing processes, the resolution of photoresist patterns begins to blur at about 45 nanometer (nm) half-pitch due to diffraction. In order to continue to use purchased manufacturing equipment of larger technology nodes, multiple exposure methods have been developed. [0005] Multiple exposure or multiple patterning techniques (MPT) involve the sequential use of two or more different masks to form patterns on a single layer of a substrate. If only two masks are used to pattern the layers, the technique is called double expos...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
CPCG06F30/398G06F2111/04
Inventor 林彥宏黄正仪徐金厂林宏隆
Owner TAIWAN SEMICON MFG CO LTD