Semiconductor package and manufacturing method thereof

Abstract

The invention provides a semiconductor package and a manufacturing method thereof. The semiconductor package comprises the components of: a first semiconductor chip, a second semiconductor chip, packaging colloid, a wiring pad, a first sub-welding line, a second sub-welding line, a first additional layer structure and a second additional layer structure. The first semiconductor chip is provided with a first acting surface and a first non-acting surface which oppose each other. The second semiconductor chip is provided with a second acting surface and a second non-acting surface which oppose each other. Furthermore the semiconductor chip is placed on the first non-acting surface through the second non-acting surface. The packaging colloid packages the first semiconductor chip and the second semiconductor chip. The first sub-welding line and the second sub-welding line are embedded into the packaging colloid and are respectively connected with a second electrode pad and the wiring pad. The first additional layer structure and the second additional layer structure are respectively formed on the two surfaces. The semiconductor package and the manufacturing method can effectively reduce planar dimension of the package and improves yield.

Description

technical field [0001] The present invention relates to a semiconductor package and its manufacturing method, especially to a semiconductor package with stacked semiconductor chips and its manufacturing method. Background technique [0002] With the evolution of semiconductor technology, semiconductor packages of different packaging types have been developed. In order to pursue the lightness, thinness and shortness of semiconductor packages, the technology of chip scale package (CSP) has been developed, which is characterized by Such chip scale packages are only equal to or slightly larger than the chip size. [0003] Figure 1A to Figure 1F The one shown is a cross-sectional view of a chip-scale package and its manufacturing method in the prior art US Pat. No. 7,202,107. [0004] Such as Figure 1A As shown, first, a carrier board 10 is provided. [0005] Such as Figure 1B As shown, then, a heat-sensitive adhesive layer 11 is formed on the carrier board 10 . [0006] ...

AI Technical Summary

Problems solved by technology

[0010] However, if the above-mentioned existing packages want to enhance product multitasking or functions, it is necessary to include multiple semiconductor chips in one package.

In the case where multiple semiconductor chips are placed adjacent to each other, the planar size of the package will be greatly increased; in addition, because of the thermal process and the filling process of the encapsulant (such as heating the encapsulant into a liquid and pouring it in), the semiconductor chip will Displacement occurs, and no matter whether the size of multiple semiconductor chips is the same, it is difficult to make the displacement of each semiconductor chip consistent, which will cause problems in the alignment of the subsequent line build-up process

[0011] Therefore, how to solve the problems of excessively large planar size of the package and different displacements of multiple semiconductor chips in the same package has become an urgent issue in the industry.

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