Input/Output Buffers for Multiple Voltage Domains
A technology of output buffer and voltage domain, which is applied in the field of electronic information, can solve the problems of affecting the performance of the input/output buffer, the area of the input/output buffer is large, and the impact is bad, so as to reduce the range of variation, improve performance, and avoid The effect of overvoltage breakdown
Active Publication Date: 2018-04-10
SHENZHEN CHIPSBANK TECH
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Problems solved by technology
Although multiple MOSs with low withstand voltage values can be superimposed to enhance its withstand voltage capability, it will inevitably cause the area of the input / output buffer to be too large, and at the same time, the ESD (Electro -Static discharge, electrostatic discharge) design is too complicated;
[0004] Second, the higher the withstand voltage value of the MOS, the higher the threshold voltage, and when the MOS with the higher threshold voltage is applied under low voltage conditions, its overdrive voltage varies with PVT (process-voltage-temperature, process-voltage-temperature) The greater the variation range caused by the change, it is easy to exceed the allowable variation range and directly affect the performance of the input / output buffer; and, for the PMOS and NMOS in the MOS, when the overdrive of the two When the voltage is affected by PVT and the direction of change is inconsistent or even completely opposite, the above effects will be even worse
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[0020] For reference and clarity, technical terms, abbreviations or abbreviations used hereinafter are summarized as follows:
[0021] MOS: Metal Oxide Semiconductor FET, Metal Oxide Semiconductor Field Effect Transistor;
[0022] PMOS: P-Metal Oxide Semiconductor FET, P-channel Metal Oxide Semiconductor Field Effect Transistor;
[0023] NMOS: N-Metal Oxide Semiconductor FET, N-channel Metal Oxide Semiconductor Field Effect Transistor;
[0024] ESD: Electro-Static discharge, electrostatic discharge.
[0025] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the ...
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This application discloses a multi-voltage domain input / output buffer, including: a pre-driver stage and a driver stage with a withstand voltage equal to the positive voltage of the highest voltage domain of the input / output buffer as the basic device, and a pre-driver stage The first power supply connected to the positive power supply input of the driver stage, the second power supply connected to the negative power supply input of the pre-driver stage, and the voltage domain identification respectively connected to the operating power, the first power supply and the second power supply The circuit is used to determine the output voltages of two power supply sources according to the output voltage of the working power supply; wherein the output voltage of the first power supply=(the output voltage of the working power supply+the positive voltage of the highest voltage domain) / 2, and the output voltage of the second power supply Output voltage = output voltage of the first power supply - positive voltage of the highest voltage domain, so as to realize input / output Multi-voltage domain design of the output buffer.
Description
technical field [0001] The present invention relates to the field of electronic information technology, more specifically, to an input / output buffer of multiple voltage domains. Background technique [0002] When MOS is used as the basic device of the input / output buffer, if the operating voltage of the input / output buffer is inconsistent with the withstand voltage value of the MOS, the following problems will exist: [0003] First, when a MOS with a low withstand voltage value is applied under high voltage conditions, overvoltage breakdown will occur. Although multiple MOSs with low withstand voltage values can be superimposed to enhance its withstand voltage capability, it will inevitably cause the area of the input / output buffer to be too large, and at the same time, the ESD (Electro -Static discharge, electrostatic discharge) design is too complicated; [0004] Second, the higher the withstand voltage value of the MOS, the higher the threshold voltage, and when the...
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IPC IPC(8): H03K19/094
Inventor 陈臣
Owner SHENZHEN CHIPSBANK TECH