Testing structure, forming method of testing structure and testing method

Abstract

The invention discloses a testing structure, a forming method of the testing structure and a testing method. The testing structure comprises a semiconductor substrate, a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer are placed on the semiconductor substrate. The first dielectric layer comprises first metal wires and second metal wires which are parallel to each other and are arrayed alternately, and both the number of the first metal wires and the number of the second metal wires are two or more. A plurality of metal plugs are placed in the second dielectric layer. The third dielectric layer comprises third metal wires and fourth metal wires which are parallel to each other and are arrayed alternately, and both the number of the third metal wires and the number of the fourth metal wires are two or more. The first metal wires and the third metal wires are perpendicular to each other on different surfaces, the second metal wires and the fourth metal wires are perpendicular to each other on different surfaces, one first metal wire is connected with one third metal wire through one metal plug, and one second metal wire is connected with one fourth metal wire through one metal plug. By means of the testing structure, resistance-capacitance delay of a plurality of metal plugs can be evaluated.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a test structure, a forming method and a test method thereof. Background technique [0002] The semiconductor manufacturing process is complex and the manufacturing cost is extremely high. In order to ensure the manufacturing quality, in the process of manufacturing semiconductor chips, test structures are usually manufactured on the wafer for testing after the manufacturing is completed. A semiconductor chip contains a plurality of metal plugs, which have a significant impact on the quality of the semiconductor chip. At present, the industry generally manufactures a metal plug test structure in a semiconductor chip. After the chip is manufactured, the metal plug test structure is used to test the production quality of the metal plug in the chip. [0003] In the existing technology, metal plugs on the same row (or column) are usually connected by upper and lo...

AI Technical Summary

Problems solved by technology

[0007] The formation method of the above-mentioned test structure can only adjust the relative position between two adjacent rows of metal plugs from the direction perpendicular to the lower metal line, and cannot adjust the position between the metal plugs from the direction parallel to the lower metal line

The position of the metal plug in the second dielectric layer can be determined by two directions: the direction perpendicular to the lower metal line and the direction parallel to the lower metal line, and only adjust the metal plug from the direction perpendicular to the lower metal line. When the position of other metal plugs around it, the adjustment range of the position of the metal plug is limited, and the accuracy of adjusting the position of the metal plug is poor

[0008] Moreover, when evaluating the resistance-capacitance delay of the metal plugs in the above test structure, the resistance of each metal plug needs to be detected separately, and the detection efficiency is low and the time cost is high.

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