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Test structure and its formation method, test method

A technology of test structure and test method, applied in the direction of semiconductor/solid-state device test/measurement, measurement electricity, measurement device, etc., can solve the problems of high time cost, low detection efficiency, poor metal plug position accuracy, etc., to simplify The effect of forming process, improving integration and reducing process cost

Active Publication Date: 2017-11-03
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The formation method of the above-mentioned test structure can only adjust the relative position between two adjacent rows of metal plugs from the direction perpendicular to the lower metal line, and cannot adjust the position between the metal plugs from the direction parallel to the lower metal line
The position of the metal plug in the second dielectric layer can be determined by two directions: the direction perpendicular to the lower metal line and the direction parallel to the lower metal line, and only adjust the metal plug from the direction perpendicular to the lower metal line. When the position of other metal plugs around it, the adjustment range of the position of the metal plug is limited, and the accuracy of adjusting the position of the metal plug is poor
[0008] Moreover, when evaluating the resistance-capacitance delay of the metal plugs in the above test structure, the resistance of each metal plug needs to be detected separately, and the detection efficiency is low and the time cost is high.

Method used

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  • Test structure and its formation method, test method
  • Test structure and its formation method, test method
  • Test structure and its formation method, test method

Examples

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Effect test

no. 1 example

[0054] This embodiment describes the method for forming the test structure in the present invention. In the test structure formed in this embodiment, the first metal pattern, the second metal pattern, the third metal pattern and the fourth metal pattern all include two metal lines .

[0055] refer to figure 1 , providing a semiconductor substrate (not shown in the figure), and forming a first dielectric layer 1 on the semiconductor substrate.

[0056] In this embodiment, the material of the semiconductor substrate can be single crystal silicon, single crystal germanium or single crystal silicon germanium, silicon-on-insulator, III-V group element compounds, single crystal silicon carbide and other materials known to those skilled in the art. semiconductors.

[0057] In addition, a device structure (not shown) may also be formed in the semiconductor substrate, and the device structure may be a device structure formed in the semiconductor front-end process, such as a MOS tran...

no. 2 example

[0097] This embodiment illustrates the test structure in the present invention.

[0098] refer to Figure 5 , is a top view of an embodiment of the test structure of the present invention, compared with the test structure in the first embodiment, the first metal pattern, the second metal pattern, the third metal pattern, and the fourth metal pattern in the test structure and a plurality of metal plugs; the first metal pattern and the third metal pattern are sequentially connected in series through the metal plugs to form a first metal chain, and the second metal pattern and the first metal pattern The four metal patterns are sequentially connected in series through the metal plugs to form a second metal chain.

[0099] Wherein, each of the first metal patterns includes two first metal lines 101 parallel to each other. Each of the second metal patterns includes two second metal lines 201 parallel to each other. The first metal line 101 and the second metal line 201 are locat...

no. 3 example

[0130] refer to Figure 6 , is a top view of another embodiment of the test structure of the present invention, the test structure includes a first metal pattern, a second metal pattern, a third metal pattern and a fourth metal pattern.

[0131] Wherein, the first metal pattern includes three first metal lines 501 parallel to each other. The second metal pattern includes three second metal lines 601 parallel to each other. The first metal line 501 and the second metal line 601 are located in a first dielectric layer (not shown) on a semiconductor substrate (not shown), the first metal line 501 and the second metal line 601 are parallel, And the second metal lines 601 and the first metal lines 501 are alternately arranged.

[0132] The metal plugs 506 and 508 are located in a second dielectric layer (not shown) on the first dielectric layer, the first metal pattern and the second metal pattern.

[0133] The third metal pattern includes three third metal lines 701 parallel to...

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Abstract

A test structure and its formation method and test method. The test structure includes: a semiconductor substrate; a first dielectric layer, a second dielectric layer and a third dielectric layer on the semiconductor substrate; the first dielectric layer includes first metal lines and second metal lines arranged in parallel and alternately , the first metal line and the second metal line are more than two; a plurality of metal plugs are located in the second dielectric layer; the third dielectric layer includes parallel and alternately arranged third metal lines and fourth metal lines, There are more than two third metal lines and fourth metal lines; the first metal line is perpendicular to the third metal line, the second metal line is perpendicular to the fourth metal line, and a first metal line passes through a metal plug The plug is connected to a third metal wire, and a second metal wire is connected to a fourth metal wire through a metal plug. The test structure provided by the present invention can evaluate the resistance-capacitance delay of a plurality of metal plugs.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a test structure, a forming method and a test method thereof. Background technique [0002] The semiconductor manufacturing process is complex and the manufacturing cost is extremely high. In order to ensure the manufacturing quality, in the process of manufacturing semiconductor chips, test structures are usually manufactured on the wafer for testing after the manufacturing is completed. A semiconductor chip contains a plurality of metal plugs, which have a significant impact on the quality of the semiconductor chip. At present, the industry generally manufactures a metal plug test structure in a semiconductor chip. After the chip is manufactured, the metal plug test structure is used to test the production quality of the metal plug in the chip. [0003] In the existing technology, metal plugs on the same row (or column) are usually connected by upper and lo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544H01L21/66G01R31/27
Inventor 曹轶宾赵简
Owner SEMICON MFG INT (SHANGHAI) CORP