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A packaging structure exposing the top surface and bottom surface of a device and its manufacturing method

A technology of packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems affecting the reliability of electrical connections, etc., and achieve the effect of improving heat dissipation and reducing volume

Active Publication Date: 2017-04-12
ALPHA & OMEGA SEMICON INT LP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Compared with another existing implementation structure (not shown in the figure) where the plane A' where the pin 6 is located is flush with the plane A where the top source 3 of the MOSFET chip 1 is located, figure 1 The package structure with plane A' lower than plane A shown has better heat dissipation effect, but because the top surface of the package structure cannot be completely attached to the plane of the integrated circuit board, it will affect the reliability of the electrical connection

Method used

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  • A packaging structure exposing the top surface and bottom surface of a device and its manufacturing method
  • A packaging structure exposing the top surface and bottom surface of a device and its manufacturing method
  • A packaging structure exposing the top surface and bottom surface of a device and its manufacturing method

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Embodiment 1

[0047] Such as Figure 4~Figure 12 The first manufacturing method of the above-mentioned package structure will be introduced, which includes the following steps:

[0048] see Figure 4 In step A1 shown, a plurality of chips 10 are formed on a wafer, each of which is a MOSFET chip, and includes top gates 11 and top sources separated from each other formed on the top surface of the wafer. 12 ( Figure 4 In the embodiment of the wafer, there are two top source electrodes 12), and a bottom drain electrode 13 formed on the bottom surface of the wafer.

[0049] see Figure 5 In the step A2 shown, on the top surface of the wafer, through ball dropping or wafer bumping and other similar processes, the top gate 11 and top source 12 of each chip 10 are correspondingly formed with protruding chips. A kind of conductive contacts 21 and 22 on the surface of 10 are used for electrical connection with external devices. The contacts on the corresponding electrodes can be formed using so...

Embodiment 2

[0064] Such as Figure 13~Figure 21 The second manufacturing method of the packaging structure of the present invention will be introduced, which includes the following steps:

[0065] Figure 13~Figure 15The steps B1 to B3 shown are similar to the steps A1 to A3 in the previous embodiment, a plurality of MOSFET chips are formed on one wafer, and each chip 10 has a top gate 11 and a top source 12 Conductive contact bodies 21 and 22 protruding from the top surface of the chip 10 are respectively formed on it, and a first plastic encapsulation body 31 is formed to cover the top surface of the chip 10 and wrap each contact body 21 and 22 therein.

[0066] In this embodiment, there is no need to grind the top surface of the wafer, but directly Figure 16 In step B4 shown, the bottom surface of the wafer is ground until the thickness y of the wafer meets the order of ultra-thin substrate (substrateless). Compare Figure 15~Figure 16 It can be seen that the thickness of the firs...

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Abstract

The invention relates to a packaging structure exposing a top surface and a bottom surface of a device and a method for manufacturing the packaging structure. The packaging structure is used for packaging a chip with thinned thickness, a top source electrode of the chip is electrically connected with a contact body and a source electrode pin in corresponding positions in sequence, and a top grid electrode is electrically connected with a contact body and a grid electrode pin in corresponding positions in sequence; a bottom drain electrode of the chip is electrically connected with a bearing part and contact parts of a frame and drain pins on the contact parts in sequence. The pins are insulated and isolated by a first plastic package body and a second plastic package body. The top surface of the packaging structure is flush and used for being electrically connected with other external devices. A bottom surface of the bearing part of the frame electrically connected with the bottom drain electrode of the chip is exposed, thereby effectively improving a heat dissipation effect of the device.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a packaging structure exposing the top surface and bottom surface of a device, and a manufacturing method of the packaging structure. Background technique [0002] At present, for example, when constructing a low-end MOSFET (Metal Oxide Semiconductor Field Effect Transistor) chip in a DC-DC converter, it is usually hoped that the top source of the MOSFET chip can be exposed on the backside of its packaging structure for convenience. While achieving circuit connection with external devices such as other chips or integrated circuit boards, the bottom drain of the MOSFET chip can also be exposed on the front of the packaging structure to improve the heat dissipation effect of the device. [0003] figure 1 Shown is a schematic diagram of an existing package structure of a semiconductor device. The bottom drain of a MOSFET chip 1 is bonded in a frame 2 whose main body is disc-shaped and...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/50H01L21/56H01L21/60H01L23/495H01L23/31H01L23/367
CPCH01L2224/32245H01L2924/13091H01L2924/00
Inventor 何约瑟薛彦迅鲁军石磊黄平赵良
Owner ALPHA & OMEGA SEMICON INT LP
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