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Counters and PLLs

A technology of counter and counting module, applied in the direction of electrical components, automatic control of power, etc., can solve the problem of large time delay of counter

Active Publication Date: 2017-11-14
LOONGSON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The main purpose of the present invention is to provide a counter and a phase-locked loop, to solve the problem that the time delay of the counter in the prior art is relatively large

Method used

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  • Counters and PLLs
  • Counters and PLLs
  • Counters and PLLs

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Embodiment Construction

[0030] It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and examples.

[0031] The embodiment of the present invention provides a counter, and the counter provided in the embodiment of the present invention is introduced in detail below:

[0032] Figure 4 is a schematic diagram of a counter according to an embodiment of the present invention, such as Figure 4 As shown, the counter in this embodiment mainly includes a first differential register 10, a second differential register 20 and a counting module 30, specifically:

[0033]The connection relationship between the first differential register 10 and the second differential register 20 is: the differential output terminal O+ / O- of the first differential register 10 is connected to the differential input termi...

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Abstract

The invention discloses a counter and a phase-locked loop. Wherein, the counter includes a first differential register, a second differential register and a counter of a counting module, wherein the first differential register is used to transmit the differential signal to the second differential register triggered by the clock signal, and the second differential register is used to transmit the differential signal to the second differential register when the clock signal is triggered. When the signal is triggered, the differential signal is reversed and then transmitted to the first differential register. The differential signal is the differential signal generated by the first differential register or the second differential register. The counting module is used to count according to the differential signal output by the first differential register. The present invention solves the problem of relatively large time delay of the counter in the prior art, and further achieves the effect of reducing the clock delay of the counter.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a counter and a phase-locked loop. Background technique [0002] The clock counter design in integrated circuits has a wide range of applications. In the prior art, the flip-flop two frequency divider structure is usually used to design the counter. figure 1 It is a circuit diagram of a counter based on a flip-flop two-frequency divider structure in the prior art. When this kind of counter is applied to a narrow pulse clock input, it has strict requirements on the pulse width. Otherwise, when an inverter is used to generate an inverted phase signal, It is difficult to guarantee the same width of the signal, which leads to the inconsistency of the opening and closing time of the register, making it difficult for the counter to form an inverse phase clock signal with exactly the same pulse width when responding to narrow pulse input. In addition, in this kind of counter, t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/18
Inventor 王峰
Owner LOONGSON TECH CORP