Semiconductor device and method for manufacturing a semiconductor device

[0011] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description, and the specific aspects in which the present disclosure can be implemented are illustrated in the accompanying drawings. In this regard, directional terms such as "top", "bottom", "front", "rear", etc. may be used with reference to the orientation of the drawings being described. Since the components of the device described can be positioned in a number of different orientations, the directional terminology can be used for illustration purposes without limitation. Without departing from the scope of the present disclosure, other aspects can be utilized and structural or logical changes can be made. Therefore, the following detailed description should not be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

[0012] As used in this specification, the terms "coupled" and/or "electrically coupled" are not intended to mean that elements must be directly coupled together. Intervening elements may be provided between "coupled" or "electrically coupled" elements.

[0013] This article describes the device and the method used to manufacture the device. Comments made in connection with the described device can also be applied to the corresponding method, and vice versa. For example, if a specific component of a device is described, the corresponding method for manufacturing the device may include the action of providing the component in an appropriate manner, even if such action is not explicitly described or illustrated in the figure. In addition, the features of the various exemplary aspects described herein may be combined with each other, unless specifically indicated otherwise.

[0014] The device according to the present disclosure may include one or more semiconductor chips. Semiconductor chips can be of different types and can be manufactured using different technologies. For example, semiconductor chips may include integrated electrical, electro-optical or electromechanical circuits, passive devices, and so on. Integrated circuits can be designed as logic integrated circuits, analog integrated circuits, mixed-signal integrated circuits, power integrated circuits, memory circuits, integrated passive devices, microelectromechanical systems, etc. For example, a semiconductor chip may include one or more power semiconductors, and may have an integrated circuit configured to control the power semiconductor(s). The power semiconductor chip may have a vertical structure in which current may flow in a direction perpendicular to the main surface of the semiconductor chip. For example, the vertical power semiconductor chip may be configured as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), JFET (Junction Gate Field Effect Transistor), etc. The source electrode and the gate electrode of the power MOSFET may be located on one face, and the drain electrode of the power MOSFET may be arranged on the other face.

[0015] The semiconductor chip need not be made of a specific semiconductor material. For example, the semiconductor chip may include at least one of Si, SiC, SiGe, GaAs, and the like. In addition, the semiconductor chip may contain inorganic and/or organic materials that are not semiconductors, such as, for example, insulators, plastics, metals, and the like. The semiconductor chip may be packaged or unpackaged, and may have a size. The thickness of the semiconductor chip may particularly be less than about 300 μm (micrometers) or less than about 250 μm (micrometers) or less than about 200 μm (micrometers) or less than about 175 μm (micrometers) or less than about 150 μm (micrometers) or less than about 125 μm (micrometers).

[0016] As used in this specification, the term "front surface" may particularly refer to the main surface of the semiconductor chip, which may include at least one of a doped region, electrical components, microelectronic components, integrated circuits, and the like. The semiconductor chip can be manufactured from a semiconductor wafer, which can serve as a substrate for microelectronic devices to be built in and on the semiconductor wafer. Integrated circuits can be manufactured by doping, ion implantation, material deposition, photolithography patterning, and the like. Manufacturing actions can generally be performed on a specific main surface of the semiconductor wafer, which may also be referred to as the "front side" of the semiconductor wafer. After the individual semiconductor chips are separated from the semiconductor wafer, the "front side" of the semiconductor wafer may thus become the "front side" of the separated semiconductor chip.

[0017] The term "backside" of the semiconductor chip may refer to the main surface of the semiconductor chip that can be arranged opposite to the front surface of the semiconductor chip. The backside of the semiconductor chip may be free of electronic components, that is, it may be mainly composed of semiconductor materials. Even though the back surface of the semiconductor chip may not be processed similarly to the front surface of the semiconductor chip, the back surface may include contact pads that provide electrical coupling to the internal electronic structure of the semiconductor chip. The front surface and the back surface of the semiconductor chip may be connected by at least one side surface extending from the front surface to the back surface.

[0018] The dicing process can be used to manufacture devices according to the present disclosure. In particular, the dicing process can be used to separate a semiconductor wafer into a plurality of semiconductor chips. At this point, appropriate dicing techniques, such as plasma etching techniques, can be applied. The dicing process can generally be performed before or after the thinning of the semiconductor wafer. In the latter case, the etched trench may extend from the front side of the semiconductor wafer to the back side of the semiconductor wafer. In the former case, trenches can be etched on the front side of the semiconductor wafer, where the trenches may not necessarily extend completely to the backside of the semiconductor wafer. Then, the semiconductor wafer can be thinned by removing the semiconductor material from the backside of the semiconductor wafer until the semiconductor wafer is separated at the location of the previously formed trench. Any suitable technique may be used to remove the semiconductor material from the backside of the semiconductor wafer, for example, at least one of grinding, polishing, and the like.

[0019] The term "plasma etching" may refer to any suitable etching or dicing technique using plasma, such as reactive ion etching, deep reactive ion etching, ion beam etching, and the like. In plasma etching, a mask material can be used to mask the semiconductor wafer, thereby leaving open areas between individual semiconductor chips (or dies). The masked semiconductor wafer can then be processed using a reactive gas plasma, which can etch semiconductor wafer material exposed between the semiconductor chips. The plasma etching may be performed by ionizing the gas mixture in the cavity to obtain ions that can react with the target material. The ionization of the gas used can be performed using radio frequency excitation emitted by the electrodes. The plasma source (or type of etching) used can be charged (ion) and/or neutral (atoms and groups of atoms). During the plasma etching process, the plasma may generate volatile etching products from chemical reactions between the elements of the material to be etched and the reaction species generated by the plasma. The atoms of the processed element can embed themselves on or under the surface of the target material, so that the physical properties of the target material can be modified.

[0020] The chemical composition of the gas used for the plasma etching action can particularly depend on the material to be etched. For example, halogen (fluorine, chlorine, bromine or iodine) gas or halogen-containing gas can be used, in which one or more additional gases can be added to improve the etching quality (such as etching anisotropy, mask selectivity, uniform etching Sex, etc.). For example, gases including fluorine (such as, for example, SF 6 , F 2 Or NF 3 ) Can be used to etch silicon. Gases including chlorine and/or bromine may be used to etch III-V materials.

[0021] The semiconductor chip included in the device according to the present disclosure may have undulations that may be particularly located at one or more side surfaces of the semiconductor chip. For example, the side surface of the semiconductor chip may fluctuate in an amplitude from, for example, about 100 nm to, for example, about 5 μm (micrometers) or from, for example, about 100 nm to, for example, about 500 nm. The fluctuation may be caused by a plasma etching process that may have been used to separate the semiconductor chip from the semiconductor wafer. For example, a time-modulated two-stage etching process can be used to etch trenches (or grooves) into the semiconductor wafer where the semiconductor wafer is to be separated. The process may include: a first stage in which an isotropic plasma etching action may be performed; and a second stage in which a passivation layer that may be configured to protect the sidewall of the trench during the etching action may be deposited. The etching action of the first stage and the deposition action of the second stage may be repeated multiple times, causing multiple etching actions to occur at the bottom of the trench, causing the mentioned wave (or wave or wave shape) of the side surface. For example, the actions of the first and second stages may be repeated from, for example, about 10 times to, for example, about 100 times. The amplitude of the fluctuations and the depth of the etched trench 9 may particularly depend on the number of repetitions of the actions of the first and second stages. In particular, the amplitude of the fluctuation can be reduced as the number of repetitions increases (for a given thickness of the semiconductor wafer to be etched).

[0022] The use of processes such as sawing or laser dicing for separating semiconductor wafers may cause damage to the semiconductor material at the side surfaces of the semiconductor chips. Such damage can be avoided at least in part by using an etching process to separate semiconductor wafers. For example, a plasma etching process can be used in this regard. In one example, the side surface of the semiconductor chip may remain free of defects extending from the side surface into the semiconductor material. In another example, a defect extending from the side surface into the semiconductor material may occur, wherein the size of the defect may be less than, for example, about 20 μm (micrometer) or less than, for example, about 10 μm (micrometer) or less than, for example, about 5 μm (micrometer). However, the application of, for example, mechanical or laser dicing techniques to the separated semiconductor wafers may result in defects in the semiconductor material that extend from the side surface into the separated semiconductor chips. Directly after the cutting process, the defect may have a size of, for example, about a few microns up to, for example, about 100 μm (micrometers). After further thermal stress and/or application of stress, which may occur during further manufacturing actions and/or operations of the separated semiconductor chip, this defect may increase up to hundreds of microns.

[0023] Scribing can be used to manufacture devices according to the present disclosure. The scribe line may be arranged between the semiconductor chips (or dies) on the front side of the semiconductor wafer, and may indicate the position where the semiconductor wafer is to be separated into individual semiconductor chips through a dicing process. In particular, the scribe line may be free of metal that has been used during the production of the electronic structure of the semiconductor chip. The scribe line may have a width from, for example, about 5 μm (micrometers) to, for example, about 100 μm (micrometers) or from, for example, about 15 μm (micrometers) to, for example, about 50 μm (micrometers). The width of the scribe line may particularly depend on the alignment properties and/or sensitivity of the semiconductor chip and/or the alignment properties of the lithography level used. Referring again to the previously described plasma etching process, the layout of the scribe lines can be (substantially) similar to the layout of the etching mask used for the etching process.

[0024] Figure 1A to 1E A method for manufacturing a device according to the present disclosure is schematically illustrated. Combine Figure 4A to 4F Describe a similar but more detailed approach.

[0025] in Figure 1A In this, a semiconductor wafer 11 having a front surface 13 may be provided. Figure 1A A cross-sectional side view of the semiconductor wafer 11 is shown.

[0026] Figure 1B A top view of the semiconductor wafer 11 is shown. The semiconductor wafer 11 may include a plurality of semiconductor chips 12. in Figure 1B In the example of, for simplicity, only four semiconductor chips 12 are shown. However, the actual number of semiconductor chips 12 formed on the semiconductor wafer 11 may vary.

[0027] in Figure 1C In this case, the first scribe line 14A may be formed on the front surface 13 of the semiconductor wafer 11. For example, the first scribe line 14A may separate the semiconductor chip 12 arranged in the lower half of the front surface 13 from the semiconductor chip 12 arranged in the upper half of the front surface 13. In particular, in the area between the semiconductor chips 12, the first scribe line 14A may have a first width w that may be substantially constant. 1.

[0028] in Figure 1D In this case, the second scribe line 14B may be formed on the front surface 13 of the semiconductor wafer 11. For example, the second scribe line 14B may separate the semiconductor chip 12 arranged in the left half of the front surface 13 from the semiconductor chip 12 arranged in the right half of the front surface 13. In particular, in the area between the semiconductor chips 12, the second scribe line 14B may have a second width w which may be substantially constant. 2. The first scribe line 14A and the second scribe line 14B may form an intersection area A. in Figure 1D In the example of, the outline of the intersection area A has an octagonal shape. The intersection area A may be greater than the first width w 1 And the second width w 2 The product of, which can correspond to the area of ​​rectangle B.

[0029] in Figure 1E Here, the semiconductor wafer 11 can be plasma-etched in the intersection area A. The plasma etching process is indicated by arrows.

[0030] Figure 2A To 2E schematically illustrates a method for manufacturing a device according to the present disclosure. Combine Figure 4A to 4F Describe a similar but more detailed approach.

[0031] in Figure 2A In this, a semiconductor wafer 11 having a front surface 13 may be provided. Figure 2A A cross-sectional side view of the semiconductor wafer 11 is shown.

[0032] Figure 2B A top view of the semiconductor wafer 11 is shown. The semiconductor chip 12 can be formed from the semiconductor wafer 11. in Figure 2B In the example of, for simplicity, only four exemplary semiconductor chips 12 are shown. However, the actual number of semiconductor chips 12 formed from the semiconductor wafer 11 may vary. The profile of at least one of the semiconductor chips 12 on the front surface 13 of the semiconductor wafer 11 may include beveled corners and/or rounded corners. in Figure 2B In the example of, the semiconductor chip 12 at the upper left may include a bevel 15. However, in another example, the semiconductor chip 12 may include rounded corners instead. In another example, one or more of the additional semiconductor chips 12 may also include beveled corners and/or rounded corners.

[0033] in Figure 2C In this, the semiconductor wafer 11 can be plasma-etched in an area that can be at least partially restricted by the bevel 15 and/or the rounded corner. The plasma etching process is indicated by arrows.

[0034] Figure 3A with 3B The top views of devices 300A and 300B according to the present disclosure are schematically illustrated. For example, the devices 300A and 300B may be manufactured by one of the previously described methods.

[0035] The device 300A may include a semiconductor chip 12, wherein the outline of the front surface 13 of the semiconductor chip 12 may include a bevel 15.

[0036] The device 300B may include a semiconductor chip 12, wherein the outline of the front surface 13 of the semiconductor chip 12 may include rounded corners 16.

[0037] in Figure 3A with 3B In the example, the corresponding semiconductor chip 12 only includes one bevel or rounded corner. In another example, the semiconductor chip 12 may include multiple beveled corners and/or multiple rounded corners.

[0038] Figure 4A to 4F A method for manufacturing a device according to the present disclosure is schematically illustrated. in Figure 4F A cross-section of an exemplary manufactured device 400 obtained by this method is shown in. The details of the device manufactured according to the described method may be equally applicable to any other device according to the present disclosure. In addition, Figure 4A to 4F The method shown in can be viewed as Figure 1A to 1E Method or Figure 2A to 2C The realization of the method. Therefore, the details of the manufacturing method described below may be equally applicable to one of the previously described methods.

[0039] in Figure 4A In this, a semiconductor wafer 11 having a front surface 13 and a back surface 17 may be provided. The semiconductor wafer 11 may be made of any semiconductor material and may have various sizes. For example, the thickness t of the semiconductor wafer 11 1 It may be less than about 800 μm or less than about 700 μm or less than about 600 μm or less than about 500 μm or less than about 400 μm or less than about 300 μm or less than about 200 μm or for example less than about 150 μm. The thickness t of the semiconductor wafer 11 can be subsequently reduced by removing the semiconductor material from the back surface 17 of the semiconductor wafer 11 1.

[0040] Figure 4B A top view of a part of the semiconductor wafer 11 (ie, a part of the front surface 13) is illustrated. One or more semiconductor chips (or dies) 12 may be formed on the semiconductor wafer 11. For simplicity, only nine semiconductor chips 12 are shown. However, the actual number of semiconductor chips 12 formed on the semiconductor wafer 11 may vary. The front side of each semiconductor chip 12 may include at least one of a doped region, electrical components, and integrated circuits. For example, manufacturing the semiconductor chip 12 and the integrated circuits included therein may include at least one of doping, ion implantation, deposition of materials, photolithography patterning, and the like.

[0041] The semiconductor chip 12 can vary in shape and size. In particular, the semiconductor chip 12 may be made according to the shape of the scribe line 14 that can be formed on the front surface 13 between the semiconductor chips 12. The scribe line 14 may indicate the position where the semiconductor wafer 11 is to be separated into individual semiconductor chips 12 later. in Figure 4B In the example, the semiconductor chip 12 may have a substantially rectangular shape, which includes a 1 And l 2 The side. Length l 1 And l 2 Can be different from each other or can be similar. Length l 1 And l 2 Each of them may be in a range from about 400 μm (micrometers) to about 1400 μm (micrometers) or from about 500 μm (micrometers) to about 1300 μm (micrometers) or from about 600 μm (micrometers) to about 1250 μm (micrometers). In a specific example, the length l 1 It can be, for example, about 1100 μm (micrometers), and the length is l 2 It may be, for example, about 625 μm (micrometers).

[0042] in Figure 4B In the example of, the scribe line 14 may form a substantially rectangular lattice that divides the semiconductor wafer 11 into a plurality of semiconductor chips 12. In another example, the crystal lattice may have a different form, such as a diamond pattern. in Figure 4B In the example, the scribe line 14 is shown as a straight line. However, the scribe line 14 may also have a different shape. For example, one or more of the scribe lines 14 may be curved, wavy, wavy, and so on. The scribe line 14 may be formed between the semiconductor chips 12 and may intersect at the intersection 18. The scribe line 14 may be formed such that the outline of the semiconductor chip 12 may include an arc-shaped line. Therefore, the corner 16 of the semiconductor chip 12 may be rounded. For example, the outline of the semiconductor chip 12 may be Figure 3B The outline of the semiconductor chip 12 in is similar.

[0043] In one example, the arc-shaped line may include or may correspond to the arc of a circle. For illustration purposes, an exemplary circle C is illustrated in one of the semiconductor chips 12. Circle C may have from about 80 μm (micrometers) to about 90 μm or from about 75 μm (micrometers) to about 95 μm (micrometers) or from about 70 μm (micrometers) to about 100 μm (micrometers) or from about 65 μm (micrometers) to about 105 μm ( Μm) radius r. In another example, the radius r may even be less than about 65 μm (micrometers) or even greater than about 105 μm (micrometers).

[0044] in Figure 4B In the illustrated example, each of the illustrated semiconductor chips 12 may include four rounded corners. In another example, each of the semiconductor chips 12 may include a different number of rounded corners according to the respective overall shape of the semiconductor chips 12.

[0045] In another example, the scribe line 14 may be formed such that the outline of the semiconductor chip 12 may include a fold line including two line segments joined together at an internal angle greater than 90°. That is, the corners of the semiconductor chip 12 may be inclined. In this case, the outline of the semiconductor chip 12 can be Figure 3A The outline of the semiconductor chip 12 is similar. The size of the bevel can be similar to the size of the rounded corner as described above. In another example, the outline of the semiconductor chip 12 may include combined rounded corners and beveled corners.

[0046] versus Figure 4B An alternative semiconductor wafer (not shown) that is different from the semiconductor wafer 11 shown in may include scribe lines 14 that may be arranged so that the corners of the semiconductor chip 12 may be rectangular at the intersection 18. in Figure 4B In, this alternative arrangement consists of Figure 4B The dashed line at the intersection 18 at the upper left side of is indicated, where the alternate intersection 18 between the alternate scribe lines 14 may be similar to a rectangle. For example, the first scribe line 14 may have a width w 1 And the second scribe line 14 may have a width w 2 , So that the surface area of ​​the rectangular intersection can correspond to the first width w 1 And the second width w 2 The product of. As from Figure 4B It can be seen that the surface area of ​​the rectangle is smaller than the surface area of ​​the intersection area formed by the semiconductor chip 12 including rounded corners.

[0047] Width of line 14 w- 1- And w 2 They can be similar, but they can also be different from each other. Width w 1 And w 2 Each of them may be in a range from about 5 μm (micrometers) to about 100 μm (micrometers) or from about 15 μm (micrometers) to about 50 μm (micrometers) or from, for example, about 10 μm (micrometers) to, for example, about 30 μm (micrometers). In one example, one or both widths w 1 And w 2 It may have a value of, for example, about 17.5 μm (micrometers).

[0048] in Figure 4C In this case, a structured mask 19 of etching resistant material may be arranged above (or on) the front surface 13 of the semiconductor wafer 11. The area to be etched can remain exposed from the structured mask 19. For example, the structured mask 19 may have been patterned using photolithography techniques. In particular, the shape of the structured mask 19 may be similar to or may be equal to the shape of the scribe line 14. After the structured mask 19 is arranged, the front surface 13 of the semiconductor wafer 11 may be plasma-etched. The particles of the plasma can be accelerated toward the front surface 13 of the semiconductor wafer 11 so that the particles can attack the semiconductor wafer 11 in a substantially vertical direction (see arrow).

[0049] During the plasma etching process, a trench (or groove) 20 may be formed at the location of the exposed semiconductor material (ie, at the location of the scribe line 14). in Figure 4C In the example of, the trench 20 may be formed when the semiconductor chip 12 (or its electronic structure) may have been manufactured. However, in other examples, the semiconductor chip 12 may also be formed after the trench 20 has been etched. The semiconductor wafer 11 may be etched until the trench 20 may have a size of less than about 260 μm (micrometers) or less than about 250 μm (micrometers) or less than about 240 μm (micrometers) or less than about 230 μm (micrometers) or less than about 220 μm (micrometers) or less than about 210 μm (Micrometers) or a height h less than about 200 μm (micrometers).

[0050] Such as Figure 4C The cross section of the groove 20 shown in does not have to have a rectangular shape. Instead, the (horizontal) width of the trench 20 may increase in the direction from the front surface 13 of the semiconductor wafer 11 to the back surface 17 of the semiconductor wafer 11. Therefore, the angle α between the sidewall of the trench 20 and the bottom of the trench 20 may be an acute angle. For example, the angle α may be less than about 75° or less than about 70° or less than about 65° or less than about 60° or less than about 55° or less than about 50° or less than about 45° or less than about 40° or less than about 35° or Less than about 30° or less than about 25°.

[0051] Refer again Figure 4B An alternative semiconductor wafer (not shown) has been described in which the intersection of the scribe line 14 may correspond to a rectangle having a smaller surface area than the intersection area formed by the scribe line 14 restricted by the rounded corners of the semiconductor chip 12. This replaceable semiconductor wafer can also be plasma etched, such as Figure 4C Shown in. However, the replaceable groove 20' obtainable in this case may be different from the groove 20 described above. in Figure 4C In the alternative case, the replaceable trench 20' is illustrated by a dashed line, where, in particular, the angle α'between the sidewall of the replaceable trench 20' and the bottom of the replaceable trench 20' may be greater than the previously described The angle α.

[0052] Reduced surface of rectangular intersection (see Figure 4B ) May result in a smaller opening of the replaceable trench 20' on the front surface 13 of the semiconductor wafer 11. Due to the reduced size of the opening, the number of particles attacking the semiconductor material on the bottom and sidewalls of the trench 20' can be reduced. Therefore, less semiconductor material is removed from the bottom and sidewalls of the trench 20 ′, so that the resulting angle α′ may become larger than the angle α that may be based on the increased surface area due to the rounded corners of the semiconductor chip 12.

[0053] in Figure 4D Here, the semiconductor material can be removed from the back surface 17 of the semiconductor wafer 11. For example, removing the semiconductor material may include at least one of grinding, polishing, and the like. In order to properly perform this removal, the semiconductor wafer 11 may be mounted to a carrier (not shown) with its front surface 13 to stabilize the semiconductor wafer 11 during the removal. For example, a first grinding wheel 21 that can perform a first grinding (or pre-grinding) of the back surface 17 of the semiconductor wafer 11 may be used to remove the semiconductor material. The grinding surface 22 of the first grinding wheel 21 may face the back surface 17 of the semiconductor wafer 11. By performing lateral movement (for example, by rotating the first grinding wheel 21), the moving grinding surface 22 can remove material from the back surface 17 of the semiconductor wafer 11.

[0054] By applying the pre-grinding process, the first grinding speed v 1 The thickness of the semiconductor wafer 11 is reduced. For example, the first grinding speed v 1 It may be in a range from, for example, about 1 μm (micrometer) to, for example, about 5 μm (micrometer) or from, for example, about 2 μm (micrometer) to, for example, about 4 μm (micrometer). In one example, the first grinding speed v 1 It may have a value of about 3 μm (micrometers), for example. The thickness of the semiconductor wafer 11 can be reduced so that the distance d from the back surface 17 of the semiconductor wafer 11 to the bottom of the trench 20 can be located from, for example, about 10 μm (micrometers) to, for example, about 40 μm (micrometers) or from, for example, about 20 μm (micrometers). ) To, for example, about 30 μm (micrometers).

[0055] in Figure 4E In this case, the first grinding wheel 21 can be replaced by the second grinding wheel 23. The grinding surface 22 of the second grinding wheel 23 may have a finer structure than the grinding surface 22 of the first grinding wheel 21. For example, the abrasive surface 22 may include fine diamond-shaped sand grains (or fine diamond-shaped particles). Using the second grinding wheel 23, material can be removed from the back surface 17 of the semiconductor wafer 11, and Figure 4D similar. During this second grinding process, the semiconductor wafer 11 can remain mounted until it may have been Figure 4D The carrier used in the action (not shown).

[0056] By applying the second grinding process, the second grinding speed v 2 The thickness of the semiconductor wafer 11 is reduced. For example, the second grinding speed v 2 It may be in the range from about 0.1 μm (micrometer) to about 0.5 μm (micrometer) or from about 0.2 μm (micrometer) to about 0.4 μm (micrometer). In one example, the second grinding speed v 2 It may have a value of about 0.3 μm (micrometer).

[0057] In one example, the thickness of the semiconductor wafer 11 can be reduced by using the second grinding wheel 23 so that the bottom of the trench 20 can be removed and the semiconductor wafer 11 can be separated into individual semiconductor chips 12. In another example, after removing the bottom of the trench 20, additional semiconductor material may be removed from the back surface of the semiconductor chip 12 that has been separated. For example, the thickness of the additionally removed semiconductor material may be in a range from about 10 μm (micrometers) to about 40 μm (micrometers) or from about 20 μm (micrometers) to about 30 μm (micrometers).

[0058] Thickness t of the separated semiconductor chip 12 after the second grinding process 2 It may be less than about 300 μm (micrometers) or less than about 250 μm (micrometers) or less than about 200 μm (micrometers) or less than about 175 μm (micrometers) or less than about 150 μm (micrometers) or less than about 125 μm (micrometers). The internal angle β between the back surface 17 of the semiconductor chip 12 and the side surface of the semiconductor chip 12 may be an obtuse angle. The internal angle β may have a value of approximately (180°-α). The possible values ​​of the interior angle β can become apparent from previous comments. For example, the internal angle may be greater than, for example, about 110°.

[0059] When the bottom of the trench 20 is removed and thereby the semiconductor chips 12 are separated from each other, the edges or corners on the back surface 17 of the semiconductor chips 12 (for example, at the positions of angles α and α'(see Figure 4C )) It may be broken due to the grinding process described. Compared with the geometric structure based on the angle α′, for the geometric structure based on the angle α, the probability of the edge or corner cracking during the grinding process can be reduced. In the case of angle α, the edges or corners on the back surface 17 of the semiconductor chip 12 may have been at least partially removed, and thus may be flatter and therefore less prone to cracking. That is, the increased surface area between the semiconductor chips 12 is selected (see Figure 4B ) May cause the angle α between the sidewall of the trench 20 and the bottom of the trench 20 to increase, which may in turn lead to reduced disconnection of the semiconductor chip 12 on the edge or corner of the back surface 17 and reduced damage.

[0060] Figure 4F A top view of an exemplary separated semiconductor chip 12 is illustrated. The semiconductor chip 12 may include rounded corners 16. That is, the outline of the front surface 13 of the semiconductor chip 12 may include a corresponding number of arc-shaped line segments. in Figure 4F In the example of, the semiconductor chip 12 may include four rounded corners due to its substantially rectangular shape. In another example, the semiconductor chip 12 may include a different number of rounded corners. In other examples, one or more of the rounded corners may be replaced by oblique corners, so that the outline of the front surface 13 of the semiconductor chip 12 may include a corresponding number of fold lines, which include two fold lines joined together at an internal angle greater than 90°. Line segment. Generally, the semiconductor chip 12 may include a different number of rounded corners and/or a different number of beveled corners.

[0061] One or more side surfaces of the semiconductor chip 12 extending from the back surface 17 to the front surface 13 may be plasma etched and thus may include fluctuations. For example, the fluctuation may have an amplitude from about 100 nm to about 5 μm (micrometers). In addition, due to the adopted plasma etching technique, defects in the material extending from the side surface of the semiconductor chip to the semiconductor chip 12 may have a reduced size, for example, a size less than about 20 μm (micrometers).

[0062] Although a particular feature or aspect of the present disclosure may have been disclosed with respect to only one of several embodiments, such feature or aspect may be combined with one or another of the other embodiments as may be desired and advantageous for any given or specific application. Multiple other features or aspects are combined. In addition, as far as the terms "including", "having", "with" or other variations thereof are used in the detailed description or claims, such terms are intended to include everything in a similar manner to the term "including". In addition, the term "exemplary" is only intended as an example, not as the best or optimal. For the purpose of conciseness and ease of understanding, the features and/or elements described herein are illustrated in specific dimensions relative to each other, and the actual dimensions may be substantially different from the dimensions illustrated herein.

[0063] Although specific examples are illustrated and described herein, those skilled in the art will realize that without departing from the scope of the present disclosure, various alternatives and/or equivalent embodiments may be substituted for the specific aspects shown and described . This application is intended to cover any adaptations or changes in the specific aspects discussed herein. Therefore, it is intended that the present disclosure is limited only by the claims and their equivalents.