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Composite error correction method for high-speed data acquisition system

A high-speed data acquisition and comprehensive error technology, applied in the direction of analog/digital conversion calibration/testing, can solve problems such as poor real-time performance, complex algorithms, and inability to adjust flexibly, and achieve the effects of strong versatility, improved accuracy and reliability

Active Publication Date: 2015-03-25
BEIHANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the current software correction algorithms have problems such as complex algorithms, poor real-time performance, and inability to flexibly adjust with changes in system errors to varying degrees.

Method used

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  • Composite error correction method for high-speed data acquisition system
  • Composite error correction method for high-speed data acquisition system
  • Composite error correction method for high-speed data acquisition system

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Embodiment Construction

[0020] The method of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0021] see figure 1 The shown hardware structure supporting the comprehensive error correction method used in the high-speed data acquisition system of the present invention is: including FPGA chip 1 , DSP chip 2 and DAC chip 3 . The DAC chip 3 is a D / A conversion integrated chip. The DSP chip 2 is a digital signal processor, which is a theory and technology for digitally representing and processing signals; DSP, Digital Signal Process. The interior of the DSP chip adopts the Harvard structure that separates the program and data, has a special hardware multiplier, widely uses pipeline operations, and provides special DSP instructions, which can be used to quickly implement various digital signal processing algorithms. The FPGA chip 1 is a field programmable gate array, which is a product further developed on the basis of programmable devices s...

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Abstract

The invention discloses a composite error correction method for a high-speed data acquisition system. According to the method, mismatch error estimation processing is conducted on three kinds of channels through hardware supports of an FPGA chip, a DSP chip and a DAC chip. Firstly, self-calibration test signals are generated in the data acquisition system so that error estimation can be conducted on the ADC channels; after a time error estimated value is acquired, if the time error is large, an FPGA is directly used for controlling a clock management chip to accurately adjust the phase difference of sampling clocks of ADC chips of all the channels for correction, and if the time error is smaller than adjusting accuracy of the clock management chip, a high-speed error correction algorithm on a DSP is used for processing; by the adoption of the self-adaptive error correction technology with integrated software and hardware, accuracy and reliability of error correction are improved.

Description

technical field [0001] The invention relates to the fields of data acquisition and digital communication, in particular to a comprehensive error correction method based on a combination of software and hardware for a high-speed and high-precision data acquisition system. Background technique [0002] The emergence of time-interleaved sampling technology has broken through the limitation of single-chip ADC chip (ADC drive amplifier), which has improved the data sampling rate and sampling accuracy, and promoted the development of high-speed and high-precision data acquisition technology. ADC driver amplifiers perform many important functions, including buffering, amplitude scaling, single-ended to differential and differential to single-ended conversion, common-mode offset adjustment, and filtering. ADC drivers have become an essential signal conditioning component in the data conversion stage and a key factor for an ADC to achieve its rated performance. [0003] However, the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10
Inventor 郑晨
Owner BEIHANG UNIV
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