Voltage reducing circuit and electronic product
A technology of step-down circuit and voltage divider circuit, which is applied in the direction of electrical components, adjusting electric variables, instruments, etc., can solve the problems that affect the market competitiveness of electronic products, LDO cannot provide large current, and the cost of electronic products increases, so as to improve the market Competitiveness, low circuit cost, effect of hardware cost reduction
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0021] Embodiment 1. The step-down circuit of this embodiment is mainly composed of an LDO chip and a PNP transistor Q1, etc., see figure 1 As shown, the LDO includes a voltage input pin VIN, a voltage output pin VOUT, an enable pin EN, a ground pin GND, an adjustment pin ADJ, etc. The DC power supply U is connected to the voltage input pin VIN of the LDO through a current limiting resistor R3 , the collector of the PNP transistor Q1 is connected to the voltage output pin VOUT of the LDO, the emitter of the PNP transistor Q1 is connected to the DC power supply U, and the base of the PNP transistor Q1 is connected to the voltage input pin VIN; that is, the PNP transistor Q1 The emitter of Q1 is connected to one end of the current limiting resistor R3, and the base is connected to the other end of the current limiting resistor R3. The ground pin GND of the LDO is grounded, the enable pin EN is active at a high level, and is connected to the DC power supply U.
[0022] In this e...
Embodiment 2
[0029] Embodiment 2. The step-down circuit of this embodiment is mainly composed of LDO chip and PMOS transistor Q1, etc., see figure 2 As shown, the LDO includes a voltage input pin VIN, a voltage output pin VOUT, an enable pin EN, a ground pin GND, an adjustment pin ADJ, etc. The DC power supply U is connected to the voltage input pin VIN of the LDO through a current limiting resistor R3 , the drain of the PMOS transistor Q1 is connected to the voltage output pin VOUT of the LDO, the source of the PMOS transistor Q1 is connected to the DC power supply U, and the gate of the PMOS transistor Q1 is connected to the voltage input pin VIN; that is, the source of the PMOS transistor Q1 Connect one end of the current limiting resistor R3, and connect the gate to the other end of the current limiting resistor. The ground pin GND of the LDO is grounded, the enable pin EN is active at a high level, and is connected to the DC power supply U.
[0030] In this embodiment, the voltage o...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 