Electrical level converter for high-speed dynamic random access memory (DRAM)

Abstract

The invention relates to an electrical level converter for a high-speed dynamic random access memory (DRAM). The two same electrical level converters and an inverter inv21 are adopted; the technical problems that a great difference between rising delay and falling delay of an existing electrical level converter for the DRAM exists and the speed of the DRAM is restricted are solved. According to the electrical level converter, the rising edge delay and the falling edge delay of a signal out can be completely matched.

Description

technical field [0001] The invention relates to a level shifter used in high-speed DRAM. Background technique [0002] In DRAM, in order to save power, the internal circuit generally works at a lower voltage, such as 1.1v, while the DRAM interface data voltage is relatively high, such as 1.8v. In DRAM, a very critical module is the level shifter (Level-shifter), which is responsible for raising the data from the internal voltage (such as 1.1v) to the interface voltage (such as 1.8v). The rise delay and fall delay of the traditional level shifter Level-shifter are very different, which is also a major bottleneck restricting the speed of DRAM products. Such as figure 1 As shown, the level shifter Level-Shifter of this structure will cause a serious mismatch between rising delay and falling delay. When the input signal ls_in changes from low to high (rising edge), first the n-type MOS transistor (n0) is turned on, the signal ls_out_n becomes low, and then the p-type MOS tran...

AI Technical Summary

Problems solved by technology

[0003] In order to solve the technical problem that the rise delay and fall delay of the existing level shifter used in DRAM are very different and restrict the speed of DRAM, the present invention provides a level shifter used in high-speed DRAM

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