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Structure and method for increasing power electronic packaging weld layer uniformity

A technology for electronic packaging and power improvement, which is applied in the direction of circuits, electrical components, and electrical solid devices, and can solve problems such as uneven solder layer thickness, achieve improved uniformity, improved void rate and discontinuous solder joints, and enhanced heat dissipation. The effect of transmission efficiency

Active Publication Date: 2015-04-15
ZHUZHOU CRRC TIMES SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] In view of this, the purpose of the present invention is to provide a structure and method for improving the uniformity of the solder layer in the power electronic package, which can effectively solve the technical problem of uneven solder layer thickness in the reflow soldering process of the existing power electronic module package

Method used

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  • Structure and method for increasing power electronic packaging weld layer uniformity
  • Structure and method for increasing power electronic packaging weld layer uniformity
  • Structure and method for increasing power electronic packaging weld layer uniformity

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specific Embodiment

[0048] A specific embodiment of a method for improving the uniformity of a solder layer in a power electronic package based on the above structure, comprising the following steps:

[0049] Printing a certain thickness of soft solder onto the substrate 2;

[0050] Positioning the liner 1 with the fulcrum array 4 on the substrate 2 through the fixture;

[0051] Put the above-mentioned combination of substrate 2 and liner 1 into a reflow furnace, perform high-temperature reflow soldering according to the set temperature control program, and form a layer of solder layer 3 with uniform thickness and controllable thickness between the liner 1 and substrate 2 .

[0052] Another specific embodiment of the method for improving the uniformity of the solder layer in the power electronic package based on the above structure includes the following steps:

[0053] Printing a certain thickness of soft solder onto the substrate 2 with the fulcrum array 4;

[0054] Positioning the liner 1 on...

Embodiment 1

[0059] as attached figure 2 , attached image 3 And attached Figure 4 As shown, the structure for improving the uniformity of the solder layer in the power electronic package in this embodiment includes: a lining board 1 , a substrate 2 , a solder layer 3 and a fulcrum array 4 . Wherein, the liner 1 and the substrate 2 are connected through the solder layer 3 , the fulcrum array 4 is located inside the solder layer 3 , and the fulcrum array 4 is arranged in a certain rule inside the solder layer 3 . The liner 1 is a ceramic liner.

[0060] The structure of the fulcrum array 4 is attached around the first metal layer 11 on the back side of the liner 1 . The soldering layer 3 is located between the lining board 1 and the substrate 2 and connects the lining board 1 and the substrate 2 . The fulcrum array 4 is located inside the solder layer 3 and is completely covered by the solder layer 3 . The fulcrum arrays 4 are located at the four corners of the first metal layer 11 o...

Embodiment 2

[0063] as attached Figure 5 As shown, the structure for improving the uniformity of the solder layer in the power electronic package in this embodiment includes: a lining board 1 , a substrate 2 , a solder layer 3 and a fulcrum array 4 . Wherein, the liner 1 and the base plate 2 are connected through the solder layer 3 , the fulcrum array 4 is located inside the solder layer 3 , and the fulcrum array 4 is arranged in a certain rule inside the solder layer 3 . The liner 1 is a ceramic liner.

[0064] The structure of the fulcrum array 4 is attached around the first metal layer 11 on the back side of the liner 1 . The soldering layer 3 is located between the lining board 1 and the substrate 2 and connects the lining board 1 and the substrate 2 . The fulcrum array 4 is located inside the solder layer 3 and is completely covered by the solder layer 3 . The fulcrum arrays 4 are located at the four corners of the first metal layer 11 on the back of the backing board 1 and connec...

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Abstract

The invention discloses a structure and method for increasing power electronic packaging weld layer uniformity. The structure comprises a lining plate, a substrate, a weld layer and a fulcrum array. The lining plate and the substrate are connected through the weld layer. The fulcrum array is disposed in the weld layer. The structure has the advantages that due to the fact that the fulcrum array is disposed in the weld layer, flowability of the weld layer during reflow welding can be increased effectively, the technical problem that the weld layer of existing power electronic module packaging is uneven in a large-area reflow welding process is solved, internal voidage and non-continuous welding points of the weld layer can be improved at the same time, thermal resistance of a power electronic module can be lowered, and the structure is simple in process, low in cost and high in operability.

Description

technical field [0001] The invention relates to the field of electronic device packaging, in particular to a structure and method for improving the uniformity of soldering layers in power electronic packaging, which are applied to power semiconductor module packaging. Background technique [0002] At present, in the power semiconductor module packaging process, the reflow soldering process is one of the main processes for power electronic module packaging, and the soft solder paste reflow soldering is a key step to realize the electrical connection between different electrical components, such as: semiconductor chips and ceramic linings The vacuum reflow soldering process is generally used between the board, the ceramic liner and the substrate. as attached figure 1 As shown, the existing power semiconductor module package includes a substrate 1 and a substrate 2 , with a solder layer 3 between the substrate 1 and the substrate 2 . Usually, due to the influence of the visco...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/498H01L21/60
CPCH01L23/3735H01L2924/19107H01L21/4853H01L23/49833
Inventor 刘国友吴义伯戴小平王彦刚
Owner ZHUZHOU CRRC TIMES SEMICON CO LTD