Jitter circuit for high-precision analogue to digital converter

Abstract

The invention discloses a jitter circuit for a high-precision ADC (Analogue to Digital Converter). The jitter circuit comprises a settable pseudo random sequence generator, a trimming module, a trimmable DAC (Digital to Analogue Converter) circuit, a jitter signal leading-in circuit and a jitter signal removing circuit, wherein the settable pseudo random sequence generator is used for generating a settable pseudo random sequence signal irrelevant to an analogue input signal Vi, and extracting an n-bit signal from the settable pseudo random sequence signal as a digital jitter signal; the trimming module is used for accurately positioning trimming signals for controlling the trimmable DAC circuit to calibrate the trimmable DAC circuit; the trimmable DAC circuit is controlled by the trimming signals to convert the received digital jitter signal into an analogue jitter signal; the jitter signal leading-in circuit is used for receiving the analogue jitter signal and the analogue input signal Vi, processing and outputting the analogue signals, and introducing the analogue signals to the input of the ADC; the jitter signal removing circuit is used for receiving the digital jitter signal, and removing the jitter signal from the output of the ADC to obtain a final data output result DOUT. According to the jitter circuit, the complexity of a high-precision ADC system can be effectively reduced, and the jitter circuit is applied to the improvement of dynamic nonlinearity of the high-precision ADC.

Description

technical field [0001] The invention belongs to the field of analog-to-digital converters, in particular to a dithering circuit used in high-precision analog-to-digital converters. Background technique [0002] In communication systems, whether it is a wideband or narrowband receiver, it is often necessary to deal with small signals that are far below the full scale, and the analog-to-digital converter is required to have a good spurious free dynamic range (Spurious Free Dynamic Range, SFDR). [0003] In a high-speed high-precision analog-to-digital converter (Analog to Digital Converter, ADC), the SFDR performance is mainly limited by two factors: one is the distortion generated by the front-end amplifier and the sample-and-hold circuit; the other is caused by the non-linearity of the ADC transfer function Distortion, namely differential nonlinearity (Differential nonlinearity, DNL). When the input signal amplitude is small, the front-end amplifier and the sample-and-hold ...

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Problems solved by technology

[0005] However, the inventors of the present invention have found through research that in actual circuits, it is very difficult to effectively remove the jitter signal, and it is required that the jitter signal sent into the analog front end, that is, the analog quantity converted by the DAC, be compared with the digital domain removed The dither signal is equal; otherwise, the output result will contain a lot of information about the dither signal, which will increase the noise floor of the ADC

This undoubtedly increases the requirements for DAC accuracy, and requires the DAC converter to have the same quantization bits as the ADC converter, which is equivalent to integrating a DAC converter with the same resolution as the ADC converter in the ADC converter. When the ADC converter When the number of quantization bits is very high, the complexity of the ADC converter system will be greatly increased, so this technology is limited in the application of high-precision analog-to-digital converters

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