Package structure and fabrication method thereof
A technology of packaging structure and manufacturing method, applied in printed circuit manufacturing, semiconductor/solid-state device manufacturing, printed circuit, etc., can solve the problems of poor electrical properties, contact offset, and difficult to control dimensional variation, so as to avoid contact offset. , The effect of improving product yield
Inactive Publication Date: 2015-04-29
SILICONWARE PRECISION IND CO LTD
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Problems solved by technology
[0007] However, in the existing package stack structure 1, the copper pillars 13 are formed by electroplating, so that the dimensional variation is difficult to control, so the heights of the copper pillars 13 are prone to inconsistencies, thus causing the problem of contact offset, causing these conductive The component 17 is in poor contact with these copper pillars 13, resulting in poor electrical performance, thus affecting product yield
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[0033] The implementation of the present invention will be described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.
[0034] It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. Limiting conditions, so there is no technical substantive meaning, any modification of structure, change of proportional relationship or adjustment of size, without affecting the effect and purpose of the present invention, should still fall within the scope of the present invention. The disclosed technical content must be within the scope covered. At the same time, terms such as "upper", "t...
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A package structure is disclosed, which includes: a first substrate; a build-up layer formed on and electrically connected to the first substrate and having a cavity; at least an electronic element disposed in the cavity and electrically connected to the first substrate; a stack member disposed on the build-up layer so as to be stacked on the first substrate; and an encapsulant formed between the build-up layer and the stack member. The build-up layer facilitates to achieve a stand-off effect and prevent solder bridging.
Description
technical field [0001] The present invention relates to a packaging structure, especially a packaging structure that can improve stacking yield. Background technique [0002] With the evolution of semiconductor packaging technology, different packaging types have been developed for semiconductor devices. In order to improve electrical functions and save packaging space, multiple packages are stacked to form a package stack structure (Package on Package) , POP), this packaging method can play the heterogeneous integration characteristics of the system in package (SiP), and can integrate electronic components with different functions, such as: memory, central processing unit, graphics processor, image application processor, etc., through stack design It achieves system integration and is suitable for various thin and light electronic products. [0003] Generally, the package stack structure (PoP) only uses solder balls to stack and electrically connect the upper and lower pac...
Claims
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IPC IPC(8): H01L23/498H01L23/31H01L21/60H01L21/56H01L25/16H01L25/00
CPCH01L23/49822H01L23/49833H01L23/3121H01L23/3135H01L2924/12042H01L24/13H01L24/16H01L24/48H01L25/105H01L2224/131H01L2224/16227H01L2224/48227H01L2224/73204H01L2225/1058H01L2924/00014H05K1/181H05K1/183H05K3/284H05K2201/10515H05K2201/10674H01L23/13H01L23/5384H01L23/5385H01L23/5389H01L2924/181H01L2225/1011H01L2924/00H01L2924/014H01L2224/45099H01L2924/00012
Inventor 陈嘉成孙铭成沈子杰洪良易萧惟中白裕呈邱士超江东昇张翊峰王隆源
Owner SILICONWARE PRECISION IND CO LTD