Systems and methods for designing layouts for semiconductor device fabrication

Abstract

The present invention provides systems and methods for designing semiconductor device layouts. For example, an initial layout including a plurality of target components associated with a semiconductor device is received. Determines one or more pseudo-parts that will be inserted into the initial layout. Target features and dummy features are assigned to the plurality of masks based at least in part on one or more mask assignment rules. A final layout for fabricating the semiconductor device is produced.

Description

technical field [0001] The technology described in this patent document relates generally to semiconductor devices, and more specifically, to the manufacture of semiconductor devices. Background technique [0002] Modern semiconductor devices are typically fabricated on integrated circuit (IC) chips. Typically, software tools can be applied to design layouts on IC chips with very small dimensions. Once a designed layout for an IC chip is complete, the layout can be converted into a set of masks or reticles using electron beam, ion beam, or other suitable techniques. During one or more photolithography processes, one or more semiconductor wafers may be patterned using a mask set such that the mask pattern is transferred to the wafer for semiconductor devices used to fabricate IC chips. [0003] As multiple devices are included on a single IC chip, the size of each device and the gap between devices (ie, feature size) continue to decrease. For example, the feature size of a...

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Problems solved by technology

[0004] However, layouts done according to specific design rules may not be reproduced on semiconductor wafers used to manufacture IC chips

For example, light can scatter causing sharp corners of shapes in the layout to appear as arcs on the wafer

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