Unlock instant, AI-driven research and patent intelligence for your innovation.

CMOS circuit structure, its manufacturing method, display substrate and display device

A technology of circuit structure and manufacturing method, which is applied in the manufacturing of circuits, electrical components, semiconductor/solid-state devices, etc., can solve the problems of threshold voltage drift, high production cost, and complicated manufacturing process in the NMOS region, so as to improve the threshold voltage drift, The effect of reducing defects and improving performance

Active Publication Date: 2017-11-10
BOE TECH GRP CO LTD
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Because the manufacturing process of CMOS circuits using LTPS technology is more complicated and the production cost is higher, therefore, the use of LTPS technology to make the semiconductor layer in the PMOS region of the CMOS circuit and the use of metal oxide materials to make the semiconductor layer in the NMOS region of the CMOS circuit have emerged. However, there is a serious drift phenomenon in the threshold voltage of the NMOS region in the CMOS circuit made by the manufacturing process (such as figure 1 shown), the performance of the NMOS region in this CMOS circuit is not stable

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • CMOS circuit structure, its manufacturing method, display substrate and display device
  • CMOS circuit structure, its manufacturing method, display substrate and display device
  • CMOS circuit structure, its manufacturing method, display substrate and display device

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0069] Example 1: The manufacturing method of both the NMOS region and the PMOS region in the CMOS circuit structure is a top-gate structure, including the following steps:

[0070] 1. Use PECVD to form a buffer layer 2 with a thickness of 100nm-500nm on the base substrate 1, such as Figure 7a As shown; wherein, the buffer layer 2 is a double-layer structure, the bottom layer is a silicon nitride film layer or a silicon oxynitride film layer, and the upper layer is a silicon oxide film layer;

[0071] 2. Perform high temperature annealing treatment on the buffer layer 2 at a temperature of 300°C to 800°C;

[0072] 3. On the buffer layer 2, the pattern of the amorphous silicon semiconductor layer 3 located in the PMOS region and the pattern of the metal oxide semiconductor layer located in the NMOS region, that is, the pattern of the NMOS semiconductor layer 4, are respectively formed, such as Figure 7b Shown

[0073] 4. Perform ELA treatment on the pattern of the amorphous silicon se...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to View More

Abstract

The invention discloses a CMOS circuit structure, a manufacturing method thereof, a display substrate and a display device. In the method, forming patterns of a PMOS semiconductor layer and an NMOS semiconductor layer includes: forming an amorphous silicon semiconductor layer located in a PMOS region on a base substrate The pattern of the pattern and the pattern of the metal oxide semiconductor layer located in the NMOS region; the pattern of the amorphous silicon semiconductor layer and the pattern of the metal oxide semiconductor layer are first annealed; the pattern of the polysilicon semiconductor layer is doped with P-type ions; In this way, when the amorphous silicon semiconductor layer is annealed to convert the amorphous silicon semiconductor layer into a polysilicon semiconductor layer, the metal oxide semiconductor layer is heated simultaneously by the annealing treatment so that the metal oxide semiconductor layer undergoes a regrowth process, Defects inside the metal oxide semiconductor layer can be reduced, so that the problem of threshold voltage drift in the NMOS region can be improved, and the performance of the NMOS region can be improved.

Description

Technical field [0001] The present invention relates to the field of display technology, in particular to a CMOS circuit structure, a manufacturing method thereof, a display substrate and a display device. Background technique [0002] Complementary Metal Oxide Semiconductor (CMOS) is composed of P-channel Metal Oxide Semiconductor (PMOS, Positive Channel Metal Oxide Semiconductor) and N-channel Metal Oxide Semiconductor (NMOS, Negative Channel Metal Oxide Semiconductor). constitute. [0003] Currently, Low Temperature Poly-silicon (LTPS) technology is generally used to fabricate the semiconductor layers of the PMOS region and the NMOS region in the CMOS circuit. Because the production process of using LTPS technology to make CMOS circuits is more complicated and the production cost is relatively high, therefore, the use of LTPS technology to make the semiconductor layer of the PMOS area in the CMOS circuit and the use of metal oxide materials to make the semiconductor layer of th...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238H01L21/324H01L21/477H01L27/092
Inventor 刘翔
Owner BOE TECH GRP CO LTD