A Dependency Grid-Based Instruction-Level Parallel Scheduling Method

Abstract

The invention discloses an instruction-level parallel scheduling method based on a dependency grid. The steps include: 1) Obtaining the data dependencies between instructions in the target basic block and the information of the functional units corresponding to each instruction, setting and Calculate the data dependence priority value of each instruction; 2) Divide each instruction according to the data dependence priority value and functional unit, store the divided results in grid form, and establish the relationship between the instruction and data dependence priority and functional unit Dependency grid of dependencies; 3) According to the data dependency priority of instructions in the dependency grid obtained in step 2), and the relationship between instructions and functional units, parallelism analysis between instructions is performed. The invention combines data dependence relationship and functional unit distribution relationship, can simultaneously describe the parallel relationship between instructions and the correlation with hardware structure, and has the advantages of simple implementation method, wide application range and high instruction level parallelism.

Description

technical field [0001] The invention relates to the technical field of compilation optimization, in particular to an instruction-level parallel scheduling method based on dependency grid description. Background technique [0002] In a basic block, one of the most basic associations between instructions is the data dependency constraint caused by the data flow, which determines the running result of the program. In modern pipeline processors and superscalar processors, instruction rearrangement can be used to increase code parallelism to take advantage of advanced architectures, but this instruction rearrangement technology needs to be based on understanding the parallelism between instructions in basic blocks can be carried out on the basis of Therefore, before or during instruction rearrangement, an important task is to identify the parallelism among instructions in a basic block. [0003] In the prior art, the basic method for rearranging the instructions in the basic bl...

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Problems solved by technology

[0005]1) Although this method describes the data dependencies between instructions, it does not show other correlations between instructions, especially those related to the target system hardware. Therefore, the correlation between the instruction and the hardware structure cannot be determined during the execution scheduling process;

[0006] 2) For the VLIW (Very Long Instruction Word, very long instruction word) architecture of the multi-function unit, since this method cannot reflect the correlation between the functional units caused by the different functional units between the instructions, this method is in the VLIW It is not suitable to use more aggressive or forward-looking instruction rearrangement technology in the architecture, which is not conducive to more fully exploring the parallelism between instructions in basic blocks brought about by the characteristics of the architecture;

[0007]3) For the VLIW architecture of multifunctional units, since this method cannot reflect the real-time workload of each functional unit, it cannot also reflect in real time between instructions, instructions and The relationship between functional units, so when some instructions can be executed in any one of multiple functional units, this method cannot be combined with functional unit allocation to make instruction scheduling produce more architecture-appropriate optimization results

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