A hardware-in-the-loop simulation environment model automatic generation system and method

Abstract

The invention discloses an automatic hardware-in-loop simulation environment model generating system. The system comprises an upper computer, a hardware parameter configuration module, a physical model configuration module, a logic linkage module, a signal sudden change curve injection setting module, a parameter checkout module, a model generating module and a compiling and downloading module, wherein the hardware parameter configuration module and the physical model configuration module adopt the upper computer as a model carrier, the logic linkage module is connected with the hardware parameter configuration module and the physical model configuration module, the signal sudden change curve injection setting module is connected with the logic linkage module, the parameter checkout module is connected with the signal sudden change curve injection setting module, and the model generating module is connected with the parameter checkout module. By means of the system, a simulation environment can be automatically designed, a simulation model can be automatically established, the time of a hardware-in-loop simulation test is shortened, the test framework is solidified, and meanwhile the requirement for personnel skills is lowered. In addition, the invention further discloses an automatic hardware-in-loop simulation environment model generating method.

Description

technical field [0001] The invention relates to the technical field of hardware-in-the-loop simulation, in particular to a system and method for automatically generating a hardware-in-the-loop simulation environment model. Background technique [0002] The hardware-in-the-loop simulation test system (Hardware-in-the-Loop, HiL) uses a real-time processor to run the simulation model to simulate the running state of the controlled object, and communicates with the electronic control unit (Electronic Control Unit, ECU) connection, conduct a comprehensive and systematic test on the ECU under test. In terms of safety, feasibility and reasonable cost, hardware-in-the-loop simulation testing has become a very important part of the ECU development process, which reduces the number of real vehicle road tests, shortens development time and costs, and improves the performance of ECUs. Software quality, reduce the risk of automobile factory. [0003] At present, in the hardware-in-the-...

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Problems solved by technology

[0003] At present, in the hardware-in-the-loop simulation test, the workload of simulation model building is very large, which will consume a lot of time and manpower, and due to the different levels of simulation model builders, the difficulty of simulation model debugging is also different. , resulting in a long and uncontrollable time period for the hardware-in-the-loop simulation test

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