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Flexible PRBS architecture for a transceiver

A technology for transceivers and users, applied in the direction of shaping networks, instruments, baseband system components, etc. in the transmitter/receiver, which can solve the problems of expensive and not universally applicable.

Active Publication Date: 2015-06-24
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The reason for this is that serial and parallel implementations for a PHY (e.g., 110-1) would be too expensive in terms of area, price, and power consumption to be universally applicable

Method used

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  • Flexible PRBS architecture for a transceiver
  • Flexible PRBS architecture for a transceiver
  • Flexible PRBS architecture for a transceiver

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0031] Figure 4 and 5 Example transceivers 400-A and 400-B are illustrated. as inFigure 4 As shown in the example shown in , the transceiver 400-A can be used as part of the PCS sublayer logic 202 of FIG. 3, and as Figure 5 As shown in the example of , transceiver 400-B may be used to communicate with serializer / deserializer (SERDES) devices. Other implementations may also be used with transceivers 400-A and 400-B, including implementations that omit encoder 306 and decoder 316 . In each case, transceivers 400-A and 400-B employ programmable transmit circuits 406-A / 406-B that can perform scrambling / descrambling and error checking based on user-specified or user-defined polynomials and can Receive circuit 408-A / 408-B is programmed.

[0032] go to Figure 6 , programmable transmit circuitry 406-A / 406-B and programmable receive circuitry 408-A / 408-B (hereinafter referred to as 406 and 408 ) can be seen in more detail. Circuits 406 and 408 may collectively be considered a t...

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PUM

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Abstract

An apparatus is provided. The apparatus comprises a polynomial register having a plurality of bits, a first bus, a second bus, and a transceiver that is coupled to the first bus, the second bus, and the polynomial register. The polynomial register is configured to store a user-defined polynomial, and the transceiver includes a pseudorandom bit sequence (PRBS) generator is configured to generate a scrambled signal from the user-defined polynomial and a PRBS checker that is configured to generate a descrambled signal from a second signal using the user-defined polynomial.

Description

technical field [0001] The present invention relates generally to a transceiver, and more particularly to a physical transceiver (PHY) with a flexible architecture. Background technique [0002] FIG. 1 shows an example of a conventional system 100 . In this system 100, hosts 102-1 through 102-N (for example, which may be computers, routers, or switches) are capable of communicating via communication medium 112 (for example, which may be Fiber optic, backplane or twisted pair) communicate with each other. In this example, network interfaces 104-1 through 104-N employ Ethernet on electrical backplane and more specifically 10GBase-KR. A description of 10GBase-KR can be found in Institute of Electrical and Electronics Engineers (IEEE) Standard 802.3-2008 dated December 26, 2008 and incorporated herein by reference for all purposes Medium). These network interfaces 104-1 to 104-N employ media access control (MAC) circuits 106-1 to 106-N, which are routed via media independent...

Claims

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Application Information

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IPC IPC(8): H04L25/03
CPCH04L25/03866G06F7/582H04L1/0041H03M13/1525
Inventor 硕·B·金特皮恩·R·高
Owner TEXAS INSTR INC