Grid scanning circuit, scanning driver and organic light emitting display
A grid scanning and circuit technology, applied in the direction of static indicators, instruments, etc., can solve the problems of uneven display, abnormal display, affecting display yield and display quality, etc., to improve the flipping speed and operating frequency, reduce Small current consumption, faster change effect
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0045] This embodiment provides a gate scanning circuit, which is connected to the timing signal CLK1, the timing signal CLK2, the start signal SIN, the high-level signal VGH and the low-level signal VGL; Figure 5 As shown, it includes a transistor T0, a transistor T1, a transistor T2, a transistor T3 and a transistor T4, and each transistor includes a gate, a first terminal and a second terminal; wherein:
[0046] The gate of the transistor T0 is connected to the timing signal CLK2 and the gate of the transistor T3; its first end is connected to the start signal SIN; its second end is connected to the gate of the transistor T1 ;
[0047] The first end of the transistor T1 is connected to the timing signal CLK1, and the second end is used as an output end OUT;
[0048] The gate of the transistor T2 is connected to the second terminal of the transistor T3 and the first terminal of the transistor T4; its first terminal is connected to the high-level signal VGH; its second term...
Embodiment 2
[0063] This embodiment provides a scanning driver, which is connected to the input terminal of the first timing signal 1, the second timing signal 2, and the start signal IN, and uses the N-level gate scanning circuit 113 composed of the gate scanning circuit described in Embodiment 1. ; its structure is as image 3 Shown:
[0064] The first timing signal 1 is connected to the timing signal CLK1 of the odd-numbered gate scanning circuits and the timing signal CLK2 of the even-numbered gate scanning circuits. The second timing signal 2 is connected to the timing signal CLK1 of the even-numbered gate scanning circuits and the timing signal CLK2 of the odd-numbered gate scanning circuits. according to image 3 It can be seen that after adopting the above-mentioned connection method, the timing signal CLK1 and the timing signal CLK2 in the gate scanning circuits of the first stage, the third stage, the fifth stage, the seventh stage, etc. are respectively related to the first ti...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More