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Manufacturing method and structure of trench MOS device

A manufacturing method and device technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as large capacitance and affecting device opening speed, so as to reduce dielectric constant, improve overall performance, and increase opening speed Effect

Active Publication Date: 2017-12-08
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] However, the capacitance between the gate and the drain (Cgd) of Trench MOS devices in the prior art is relatively large, namely Figure 5 The capacitance between the polysilicon 50 and the N-type epitaxial layer 10 is relatively large, thus affecting the turn-on speed of the entire device

Method used

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  • Manufacturing method and structure of trench MOS device
  • Manufacturing method and structure of trench MOS device
  • Manufacturing method and structure of trench MOS device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0043] Please refer to Image 6 , in the present embodiment, propose a kind of manufacturing method of Trench MOS device, comprise steps:

[0044] S100: Provide a trench structure, the trench structure includes a drain layer 100, a silicon layer 200 and a dielectric layer 300, the silicon layer 200 is formed on the surface of the drain layer 100, the trench structure is provided with a trench groove 110, the dielectric layer 300 is formed in the groove 110 and is in close contact with the silicon layer 200 and the drain layer 100, such as Figure 7 with Figure 8 shown;

[0045] In step S100, the trench structure is formed by the following steps, which include:

[0046] providing a drain layer 100;

[0047] forming a silicon layer 200 on the surface of the drain layer 100;

[0048] Etching the silicon layer 200 and the drain layer 100 in sequence to form a trench 110, the trench 110 exposes a part of the drain layer 100, such as Figure 7 As shown, wherein, a patterned p...

Embodiment 2

[0063] In the manufacturing method of the Trench MOS device proposed in this embodiment, the only difference from the first embodiment is that the drain layer 100 is a P-type epitaxial layer, and the silicon layer 200 is implanted with N-type ions, so that the formed silicon Layer 200 is N-type, and the formed source 700 is P + type, and other steps are the same as those in Embodiment 1. Meanwhile, the structure of the proposed Trench MOS device is also the same as Embodiment 1. Please refer to Embodiment 1 for details, and details will not be repeated here.

[0064] To sum up, in the manufacturing method and structure of the Trench MOS device provided by the embodiment of the present invention, a low-K layer is formed between the gate and the drain layer to reduce the dielectric constant between the gate and the drain layer, Therefore, the capacitance value between the gate and the drain layer is reduced, thereby increasing the turn-on speed of the Trench MOS device and impro...

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Abstract

The invention discloses a manufacturing method and a structure of a Trench MOS device. A low-k layer is formed between a gate and a drain layer to reduce the dielectric constant between the gate and the drain layer. Thus, the value of capacitance between the gate and the drain layer is reduced, the opening speed of the Trench MOS device is increased, and the overall performance of the Trench MOS device is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a manufacturing method and structure of a Trench MOS device. Background technique [0002] Since the invention of power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) technology, the technology has achieved many important developments and great progress. In recent years, new device structures and new manufacturing processes of power MOSFET technology are still emerging to achieve the two most basic goals: maximum power handling and minimum power loss. Trench MOS (vertical MOS device) is one of the most important technology pushes to achieve this goal. The biggest advantage of Trench MOS technology is that it can increase the channel density of planar devices to improve the current handling capability of devices. [0003] Please refer to Figure 1 to Figure 5 , Figure 1 to Figure 5 It is a schematic cross-sectional view of the Trench MOS device manufacturi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/78H01L29/06
CPCH01L29/0603H01L29/4236H01L29/42364H01L29/66477H01L29/78
Inventor 黄晨
Owner SEMICON MFG INT (SHANGHAI) CORP