An 8-tube sram bit cell circuit array suitable for low voltage operation
A circuit array and bit unit technology, applied in information storage, static memory, digital memory information, etc., can solve the problems of SRAM data competition, non-selected unit data interference, etc., and achieve the effect of eliminating competition and interference
Active Publication Date: 2017-11-10
SUZHOU WULI INFORMATION TECH
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Problems solved by technology
[0008] In order to solve the above-mentioned problems in the prior art, the present invention provides an 8-tube SRAM bit cell circuit array suitable for low-voltage operation, aiming to solve the problem of data competition during SRAM write operation and the problem of interference of unselected cell data
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[0030] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.
[0031] see figure 2 As shown, an 8-tube SRAM bit cell circuit suitable for low-voltage operation includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor. NMOS transistor N4, fifth NMOS transistor N5 and sixth NMOS transistor N6;
[0032] Wherein, the first PMOS transistor P1 and the first NMOS transistor N1 form a first inverter, and the second PMOS transistor P2 and the second NMOS transistor N2 form a second inverter; the first The output terminal of the inverter is directly connected to the input terminal of the second inverter, and the output terminal of the second inverter is directly connected to the input terminal of the first inverter;
[0033] The sources of the first PMOS transistor P1 and the secon...
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The invention discloses an 8-tube SRAM bit unit circuit array suitable for low-voltage operation. The 8-tube SRAM bit unit adds two NMOS tubes to the traditional 6-tube SRAM bit unit, and is controlled by two signal lines respectively; In an array composed of 8-tube SRAM bit cells, two PMOS transistors are added to each column, which are also controlled by the above two signal lines. During the write operation, by controlling the two newly added PMOS transistors in each column of the array to turn off the power supply of the bit cell, the competition relationship is eliminated, and the operation without competition is realized; Adding two control NMOS transistors eliminates interference to SRAM bit cells on unselected columns of the same row in the array. The novel circuit structure proposed by the invention can simultaneously solve the problem of data competition during SRAM write operation and the problem of unselected unit data being disturbed, so that the SRAM can work at a lower voltage.
Description
technical field [0001] The invention belongs to the technical field of semiconductor circuits and is used for memory and chip circuit design, in particular to an 8-tube SRAM bit unit circuit array suitable for low-voltage operation. Background technique [0002] Such as figure 1 as shown, figure 1 It is a schematic diagram of a traditional 6-tube (6T) SRAM bit cell array. This traditional SRAM array has the following two main disadvantages: [0003] 1. Due to the competition between the data value to be written and the saved data value in the traditional SRAM write operation, the write operation is prone to failure when the voltage is low. [0004] Assume that before the write operation: node NVB1 saves the value "1", and NV1 is "0". [0005] During the write operation, BLB1 is 0, BL1 is 1, and the node NVB1 is pulled down to "0" by the pull-down of BLB1 "0", thus causing the node NV1 to flip to "1". However, in the process of NVB1 being pulled down to "0" by BLB1, since...
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IPC IPC(8): G11C11/413
Inventor 张建杰张泳培
Owner SUZHOU WULI INFORMATION TECH