Current detection circuit and semiconductor memory apparatus

Abstract

The invention provides a current detection circuit and a semiconductor memory apparatus using the current detection circuit thereof. The current detection circuit is capable of rapidly sensing the current flowing through a tiny bit line structure. A page buffer / sensing circuit of the invention includes: a transistor TP3 pre-charging a node SNS during a pre-charge period and providing a target constant current to the node SNS during a discharge period; a transistor TN3 pre-charging the bit line according to the voltage pre-charged to the node SNS; and a transistor TP2 connected to the node SNS. The transistor TP2 detects whether or not a current larger than the constant current supplied by the transistor TP3 is discharged from the bit line and outputs a detection result to a node SENSE.

Description

technical field [0001] The present invention relates to current sensing for detecting current flowing in a bit line, and more particularly to a current detection type sensing circuit of a semiconductor memory device. Background technique [0002] figure 1 An example of a conventional bit line selection circuit and a page buffer / sensing circuit of a flash memory is shown. Here, a pair of bit lines, that is, an even bit line GBL_e and an odd bit line GBL_o are taken as an example. The bit line selection circuit 10 has an even selection transistor SEL_e connected to the even bit line GBL_e, an odd selection transistor SEL_o connected to the odd bit line GBL_o, an even bias selection transistor YSEL_e connected between the even bit line GBL_e and the virtual potential VIR, The bit line selection transistor BLS is connected to the odd bias selection transistor YSEL_o between the odd bit line GBL_o and the virtual potential VIR, and the common node N1 of the even selection trans...

AI Technical Summary

Problems solved by technology

[0007] However, such a voltage detection type sensing circuit has a problem that it is very difficult to shorten the sensing time when the bit line is finely structured.

That is to say, when the line width of the bit line or the interval between the bit lines becomes finer, the impedance of the bit line will become larger, and the capacitive coupling between the bit lines will also become larger, so it is necessary to precharge the bit line to A certain voltage is quite time consuming

In particular, in the bit line shielded read operation, the adjacent bit line is shielded to the GND potential, thus prolonging the precharge time of the selected bit line

[0008] On the other hand, the threshold value of the memory cell to be erased is not uniform, and the current flowing through the bit line is not necessarily constant during the read operation.

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