Mask read-only memory, method of making and using same
A mask read-only, memory technology, used in semiconductor/solid-state device manufacturing, electrical solid-state devices, semiconductor devices, etc.
Active Publication Date: 2018-02-06
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology
[0003] The technical problem to be solved by the present invention is to provide a mask ROM that can improve the peripheral leakage defects of the existing mask ROM and improve the stability of the device; the invention also provides a mask ROM that can improve the existing mask ROM Mask read-only memory manufacturing method for peripheral leakage defects; the present invention also provides a method for using the mask read-only memory
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[0038] Such as figure 1 As shown, the mask read-only memory provided by the present invention includes: a P well on a silicon substrate, shallow isolation grooves on both sides of the P well, a plurality of N-type buried source / drain regions on the top of the P well, and the gate oxide is located in the P well and above the shallow isolation groove, the N-type polysilicon gate is located above the gate oxide, the N-type polysilicon gate has isolation sidewalls on both sides, and there is at least one set of corresponding channel regions between the two N-type buried sources / drains under the N-type polysilicon gate and a doped channel region; also includes a P-type polysilicon gate located between the N-type polysilicon gate and the isolation sidewall, and the metal silicide on the P-type polysilicon gate and the N-type polysilicon gate realizes the gate electrode connection; wherein, the N-type polysilicon gate The doping concentration of the gate is greater than that of the N...
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The invention discloses a mask read-only memory, including a P-well on a silicon substrate. Two sides of the P-well are provided with shallow isolated grooves. The upper portion of the P-well is provided with a plurality of N-type buried source / drain region. Gate-oxide is located above the P-well and the shallow isolated grooves. An N-type polysilicon gate is located above the gate-oxide. Two sides of the N-type polysilicon gate are provided with isolation side walls. At least a set of corresponding channel regions and P-type source and drain injection regions is disposed between the two N-type buried source / drain regions below the N-type polysilicon gate. The doped concentration of the P-type source and drain injection regions is higher than that of the channel regions. The mask read-only memory is characterized by further comprising a P-type polysilicon gate located between the N-type polysilicon gate and the isolation side walls. The invention further discloses methods of manufacture and use of the mask read-only memory. The mask read-only memory can overcome the defect of electric leakage at the periphery of a conventional mask read-only memory, and improve device stability.
Description
technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a mask ROM; the invention also relates to a method for manufacturing the mask ROM and a method for using the mask ROM. Background technique [0002] Mask read-only memory (Read-Only Memory) is a memory that can only read data. In the manufacturing process, the data is burned into the circuit with a special mask (mask), and the data content cannot be changed after writing, so it is sometimes called "mask ROM" (mask ROM). The manufacturing cost of this memory is relatively low. The data of this ROM is written during production. In fact, it is very similar to the principle of a CD, and the data state is written in the photolithography process of the semiconductor. The data in this ROM is impossible to lose, and its cost is very low. MaskROM is widely used in devices that do not require data updates. The device unit of Mask rom is an N-type MOSFET (NMOS device). The cha...
Claims
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IPC IPC(8): H01L27/112H01L29/423H01L21/28H01L21/8246
Inventor 刘冬华钱文生石晶
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP