Manufacturing method for FFS array substrate
A manufacturing method and array substrate technology, applied in semiconductor/solid-state device manufacturing, optics, instruments, etc., can solve the problems of low electron mobility, large leakage current, and poor light stability of amorphous silicon, and achieve light stability and light stability. Good permeability, high electron mobility and aperture ratio, and the effect of reducing the number of photomasks
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Embodiment 1
[0038] Such as figure 1 Shown is a flowchart of a method for manufacturing an FFS array substrate in this embodiment, Figure 2 to Figure 8 Sequence diagram for fabricating the FFS array substrate for this embodiment.
[0039] From figure 1 It can be seen that a method for manufacturing an FFS array substrate in this embodiment includes the following steps:
[0040] S101: if figure 2 As shown, a gate 3 and a common electrode 2 are formed on a glass substrate 1 , and the gate 3 is formed on a part of the common electrode 2 . The specific manufacturing process is as follows: now a layer of ITO is deposited on the glass substrate 1, and then a metal layer is deposited on the ITO layer. The material of the metal layer can be copper or aluminum, or other metals. Then, the ITO layer and the metal layer are patterned once more, that is, through a photomask process, including photoresist coating, exposure, development, etching, and photoresist removal, to form the gate electrode....
Embodiment 2
[0049] The front part of this embodiment is the same as S101-S105 of Embodiment 1, the difference is that after S105, before forming the source electrode 10 and the drain electrode 11 on the semiconductor active layer 8, a step is further included: An etching stopper layer 13 is formed on the semiconductor active layer 8 and the pixel electrode 9 , and in this embodiment, the etching stopper layer 13 is preferably made of silicon oxide. In addition, via holes are formed on both ends of the semiconductor active layer 8 and on the corresponding etching barrier layer 13 on one end of the pixel electrode 9 close to the semiconductor active layer 8, so that the semiconductor active Two ends of the layer 8 and one end of the pixel electrode 9 close to the semiconductor active layer 8 are exposed to prepare for the next step of forming the source electrode 10 and the drain electrode 11 .
[0050] Next, the source electrode 10 and the drain electrode 11 are formed on the etching barri...
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