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Component with an active region under relaxed compressive stress, and associated decoupling capacitor

A technology of active areas and components, applied in the direction of capacitors, circuits, electrical components, etc., to achieve the effect of reducing compressive stress

Inactive Publication Date: 2015-11-25
STMICROELECTRONICS (ROUSSET) SAS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this requires precise design work by the designer, and most of the time only uses a small fraction of empty space

Method used

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  • Component with an active region under relaxed compressive stress, and associated decoupling capacitor
  • Component with an active region under relaxed compressive stress, and associated decoupling capacitor
  • Component with an active region under relaxed compressive stress, and associated decoupling capacitor

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Embodiment Construction

[0046] exist figure 1 In , the reference TRN designates an NMOS transistor whose active region 10 is located within a semiconductor substrate 1 made, for example, of P-doped silicon. The active region is surrounded by an insulating region 2, eg of Shallow Trench Isolation (or STI) type.

[0047] A transistor TRN forming part of an integrated circuit CI conventionally comprises a gate region 3 separated from an active region 10 by a gate dielectric OX, eg silicon dioxide. Furthermore, the gate region 3, the active region 10 and the insulating region 2 are covered by a layer of gate dielectric OX and an additional insulating region 4, which conventionally comprises a lower insulating layer 40 of eg silicon nitride, the additional insulating region 4 is also known by those skilled in the art by the acronym CESL (Contact Etch Stop Layer). The additional insulating region 4 also comprises at least one other layer, for example at least one layer 42 of silicon dioxide, on top of t...

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Abstract

An integrated circuit includes a substrate and a circuit component (such as a MOS device or resistance) disposed at least partially within an active region of the substrate limited by an insulating region. A capacitive structure including a first electrode (for connection to a first potential such as ground) and a second electrode (for connection to a second potential such as a supply voltage) is provided in connection with the insulating region. One of the first and second electrodes is situated at least in part within the insulating region. The capacitive structure is thus configured in order to allow a reduction in compressive stresses within the active region.

Description

[0001] priority [0002] This application claims priority from French Patent Application No. 1454552 filed May 21, 2014, which is hereby incorporated by reference in its entirety. technical field [0003] The present invention relates to an integrated circuit, and more particularly to the relaxation of compressive stresses in active regions, such as those of NMOS transistors, and also to the generation of embedded decoupling capacitors, in other words with Other components of the integrated circuit are formed in combination and on the same chip. Background technique [0004] In an integrated circuit, transistors are formed in and on an active semiconductor region, such as silicon, surrounded by an electrically insulating region, such as a trench filled with, for example, silicon dioxide. [0005] Forming a MOS transistor within an insulating region naturally results in the formation of an active region under compressive stress due to the presence at the periphery of the in...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/06H01L29/40H10N97/00
CPCH01L28/60H01L27/0629H01L27/0676H01L27/11524H01L27/11526H01L29/42356H01L29/66181H01L29/7842H01L29/945H01L29/94H10B41/42H10B41/35H10B41/40
Inventor S·维达尔特C·里韦罗G·鲍顿P·弗纳拉
Owner STMICROELECTRONICS (ROUSSET) SAS