Cache device for reconfigurable cryptographic processor

Abstract

The present invention discloses a caching apparatus used for reconfigurable cipher processor. The caching apparatus comprises: a data loading module, used for entering a corresponding operating mode according to configuration information and input FIFO (first in first out) data, so as to send the FIFO data to at least one data channel; a channel sequence recording cache, used for recording an input sequence of sending the FIFO data into each data channel; an output data management module, used for outputting, according to the input sequence, the FIFO data output by a processing module; and an intermediate data and feedback control module, used for entering a corresponding operating mode according to intermediate data, so as to buffer the intermediate data that needs to be further processed and buffer the intermediate data needed for array configuration. According to the caching apparatus provided by an embodiment of the present invention, the caching of different types of data needed for a cipher algorithm can be satisfied, the parallel operation capability can be improved, and a block cipher algorithm can be efficiently implemented on the reconfigurable cipher processor.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a cache device for a reconfigurable cryptographic processor. Background technique [0002] With the development of various electronic technologies, the user's demand for transmitting information technology through electronic products is increasing, and the requirements for network information security are also getting higher and higher. In order to ensure the security of these information, the data is encrypted into a row effective measures. On the basis of being able to use highly secure algorithms, the cryptographic chip design also needs to ensure that the hardware circuit itself does not contain too much key information, but the algorithm that can be implemented by traditional cryptographic chips is relatively single, which is difficult to meet the needs of different cryptographic algorithms, and The hardware structure also contains a lot of algorithm-related security in...

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Problems solved by technology

[0004] However, since the RCA scale of the reconfigurable cipher is certain, different cryptographic algorithms have different mappings to the array, and it may even occur that some structures in the algorithm need to increase the number of configurations to be mapped to the array. The data between them are related. If an external memory is used to read and write the intermediate data that needs to be called, the slow read and write speed of the external memory itself will reduce the computing performance of the reconfigurable cryptographic processor.

[0005] To sum up, the reconfigurable cipher processors in the related art cannot well realize the caching of different types of data required by the cipher algorithm, resulting in the inability to meet the efficient implementation of the block cipher algorithm on the reconfigurable cipher. Room for improvement

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