Clock signal generator, communication device and sequential clock signal gating circuit

Abstract

The present invention discloses a clock signal generator, a communication device and a sequential clock signal gating circuit. The clock signal generator comprises an oscillator for generating a reference clock signal, a multi-phase clock signal generating circuit for generating a plurality of output clock signals according to the reference clock signal and stopping or starting the output of the plurality of output clock signals according to a power supply control signal, wherein the output clock signals have the same frequency and different phases, a sequential clock signal gating circuit for sequentially stopping or starting the output of multiple gating clock signals according to a gating control signal and the multiple output clock signals and maintaining the relation of the output number of cycles of the multiple gating clock signals when the multi-phase clock signal generating circuit stops or restarts the output of the multiple output clock signals, and a clock signal working control circuit for providing the power supply control signal and the gating control signal.

Description

technical field [0001] The invention relates to the technical field of clock signal generation, application and control, in particular to a clock signal generator, a communication device and a sequential clock signal gating circuit capable of maintaining the relationship between a clock signal output cycle number. Background technique [0002] In the Ethernet communication system, the two connection terminals will play the role of the master terminal (Master) and the slave terminal (Slave) respectively according to a preset mechanism. The master terminal and the slave terminal each have a clock signal generation circuit, and the two The clock signal generation circuits work independently, and the generated clock signals are not directly related and usually have differences. However, in order for the master control terminal and the controlled terminal to decode the signals transmitted by each other, the clock signal generation circuit of the controlled terminal will first dec...

AI Technical Summary

Problems solved by technology

[0004] Based on the above, taking a device with a connection speed of 1Gigabit / s as an example, in order to comply with the EEE standard for the current Ethernet connection technology, after the two connection terminals establish the connection and determine the appropriate clock signal, they will store the established The parameters of the clock signal relationship, and the clock signal generation circuit keeps working when entering the EEE mode, so that the EEE mode can be left within the aforementioned predetermined time when there is a packet transmission requirement. However, the clock signal generation circuit in the Ethernet device It consumes a lot of power. If the clock signal generating circuit continues to work normally when it is in EEE mode, it will consume a lot of power; but if the clock signal generating circuit is turned off after entering EEE mode and then turned on when leaving EEE mode to save power, Considering that the clock signal generation circuit may output wrong clock signals (such as clock signal glitch (Clock Glitch)) when it is shut down and restarted, or lose the relative relationship of each clock signal after restarting, it will take longer for the two connection terminals to recover. Recalibrating or establishing a clock signal relationship so that normal operation cannot be resumed within the time required by the EEE specification

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