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Si-based MHEMT epitaxial structure

An epitaxial structure and epitaxial layer technology, applied in the direction of electrical components, circuits, semiconductor devices, etc., can solve the problems of difficult processing, fragile, difficult mass production, etc., to improve the problem of lattice mismatch, reduce costs, cheap effect

Inactive Publication Date: 2016-02-03
CHENGDU HIWAFER SEMICON CO LTD
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Problems solved by technology

However, the shortcomings of InP-based HEMTs are also very obvious. InP materials are expensive, and the current maximum size of InP substrates is only 2 inches, and they are fragile, difficult to process, and difficult to mass produce.
[0003] At present, in order to reduce costs, some manufacturers use GaAs substrates instead of InP substrates, but due to the limitations of the price and size of GaAs materials, mass production is still not possible.

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  • Si-based MHEMT epitaxial structure

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Embodiment Construction

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0020] see figure 1 , is a schematic diagram of a Si-based MHEMT epitaxial structure according to an embodiment of the present invention. The Si-based MHEMT epitaxial structure of this embodiment includes a P-type Si substrate 1 on which a GaAs nucleation layer 2 , a lattice strain buffer layer 3 and an epitaxial layer 4 are grown sequentially from bottom to top. The lattice strain buffer layer 3 is used to absorb the stress caused by lattice mismatch between...

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Abstract

The invention provides a Si-based MHEMT epitaxial structure. The Si-based MHEMT epitaxial structure comprises a P-type Si substrate, a GaAs nucleation layer, a lattice strain buffer layer and an epitaxial layer which sequentially grow from down to up, wherein the lattice strain buffer layer is used for absorbing stress between the P-type Si substrate and the epitaxial layer generated because of lattice mismatching, the epitaxial layer sequentially comprises a GaInAs channel layer, an AlInAs isolation layer, a Si doping layer, an AlInAs barrier layer and a GaInAs cap layer from down to up, and the lattice strain buffer layer comprises a GaAs buffer layer employing high temperature growth, a first InP buffer layer employing low temperature growth, a GaInAs stress binding layer, a second InP buffer layer employing high temperature growth, a first AlInAs buffer layer employing low temperature growth and a second AlInAs buffer layer employing high temperature growth which sequentially grow from down to up. According to the AlInAs buffer layer employing low temperature growth, heterogeneous integration of a Si material and an InP channel material can be realized.

Description

technical field [0001] The invention relates to the technical field of semiconductor device manufacturing, in particular to a Si-based MHEMT epitaxial structure. Background technique [0002] InP-based HEMT (highelectronmobilitytransistor, high electron mobility transistor) has been recognized as having great advantages in microwave / millimeter wave low-noise, high-power applications. InP-based HEMT has a very high electron mobility and two-dimensional electron gas density because the In component of the GaInAs channel can reach more than 53%, so the device performance is superior to Si-based RF CMOS devices. However, the shortcomings of InP-based HEMTs are also very obvious. InP materials are expensive, and the current maximum size of InP substrates is only 2 inches, and they are fragile, difficult to process, and difficult to mass produce. [0003] At present, in order to reduce costs, some manufacturers use GaAs substrates instead of InP substrates, but due to the price a...

Claims

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Application Information

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IPC IPC(8): H01L29/778H01L29/06H01L29/201H01L21/02
CPCH01L29/7787H01L21/02381H01L29/0684H01L29/201
Inventor 黎明
Owner CHENGDU HIWAFER SEMICON CO LTD