Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device, and the device comprises a substrate, a grid stack on the substrate, source and drain regions located at two sides of the grid stack, and contact metal layers on the source and drain regions. The device is characterized in that the contact metal layers achieve automatic isolation through the grid stack; the contact metal layers enclose the tops of the source and drain regions and at least a part of side walls of the source and drain regions. According to the invention, deep source and drain contact holes are etched and filled, thereby enabling three surfaces of the contact metal layers to enclose the source and drain regions of an MOSFET, increasing the contact area of the source and drain regions, reducing the contact resistance, and improving the strain effect.

Description

technical field [0001] The present invention relates to a semiconductor device and its manufacturing method, in particular to a three-dimensional multi-gate FinFET and its manufacturing method which can effectively improve the contact area and stress effect of a self-aligned contact structure. Background technique [0002] In current sub-20nm technologies, three-dimensional multi-gate devices (FinFET or Tri-gate) are the dominant device structure, which enhances gate control and suppresses leakage and short-channel effects. [0003] For example, compared with the traditional single-gate body Si or SOI MOSFET, the MOSFET of the double-gate SOI structure can suppress the short channel effect (SCE) and the induced leakage barrier lowering (DIBL) effect, and has a lower junction capacitance, which can To achieve light doping of the channel, the threshold voltage can be adjusted by setting the work function of the metal gate, which can obtain about twice the driving current, redu...

AI Technical Summary

Problems solved by technology

However, with the sharp reduction in device size, the source and drain regions, especially the source and drain regions of the FinFET structure, not only reduce the length in the channel direction but also reduce the lateral width to the line width of the fin structure, so that the stress-enhanced substrate The layer does not fully cover, or the liner itself is too small to achieve the required stress

[0007] In summary, the existing manufacturing methods of SAC and adjacent isolation structures cannot effectively ensure sufficient contact area and required stress effect, which needs to be improved urgently

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