The Circuit Structure and Method of Realizing Clock Recovery Based on USB Device

Abstract

The invention relates to a circuit structure and method for realizing clock recovery based on a USB device, wherein the circuit structure includes a built-in oscillator module for generating an oscillation signal; a digital control logic module; the digital control logic module includes: a USB clock recovery unit for The oscillating signal of the built-in oscillator is sampled and the clock is recovered; the frequency adjusting unit is used for adjusting the oscillating frequency of the built-in oscillator according to the comparison result of the USB signal and the oscillating signal of the built-in oscillator. The circuit structure and method for realizing clock recovery based on USB devices with this structure can generate accurate system clocks and have frequency tracking characteristics. By using digital control logic modules, the frequency of USB data transmission and the frequency of the built-in oscillator are compared. The frequency of the built-in oscillator is switched among three states of low speed, medium speed and high speed, which takes into account the accuracy and stability of the system, reduces the production cost, and has a wider range of applications.

Description

technical field [0001] The present invention relates to the field of clock recovery, in particular to the field of USB device clock recovery, in particular to a circuit structure and method for realizing clock recovery based on USB device. Background technique [0002] Most of the existing technologies are the following solutions: [0003] (1) Using an external crystal oscillator to provide an accurate clock for the circuit; [0004] (2) A phase-locked loop PLL design is adopted to generate a clock signal consistent with the frequency and phase of the serial data; [0005] (3) Adopt delay-locked loop DLL design to generate a clock signal consistent with serial data frequency and phase. [0006] Disadvantages of the above approach: [0007] (1) External crystal oscillator, the periphery is relatively complex, the error is large, and the cost is increased; [0008] (2) The PLL design of the phase-locked loop makes the circuit area relatively large, the overall design is mo...

AI Technical Summary

Problems solved by technology

[0007] (1) External crystal oscillator, the periphery is relatively complex, the error is large, and the cost is increased;

[0008] (2) The PLL design of the phase-locked loop makes the circuit area relatively large, the overall design is difficult, the locking time is long, it is sensitive to noise, and there are problems such as accumulation of phase difference errors;

[0009] (3) Delay-locked loop DLL design has poor jitter suppression performance, relatively limited locking range, high power consumption, and no frequency tracking characteristics

Images