Data processing method executed by network device and related equipment

Abstract

A data processing method executed by a network device and related equipment. A data processing method performed by a network device, comprising: an i-th processing circuit in a first circuit group receives a first message header and data D(1, i‑1), and obtains based on the first field of the first message header Data D'(1,i), and sending the first packet header and data D(1,i) to the i+1th processing circuit in the first circuit group; wherein, the data D(1,i) is based on the data D (1,i-1) and data D'(1,i) are obtained; the i-th processing circuit in the first circuit group sends data D(1,i) to the i+1-th processing circuit in the second circuit group; The i-th processing circuit in the second circuit group sends the second packet header to the i+1-th processing circuit in the second circuit group. The solutions provided by the embodiments of the present invention are beneficial to improving the utilization rate of processing resources and reducing the complexity of message processing.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to a data processing method executed by a network device and related equipment. Background technique [0002] Currently, in a packet forwarding and processing device such as a router or a switch, a network processor is usually used to implement forwarding and processing of network packets. Wherein, the network processor refers to a programmable processor specially used for processing network packets. The network processor integrates a large number of special circuits inside to improve the processing speed of network packets. [0003] According to the different implementation methods of network processors processing packets, they can be roughly divided into two categories. The first type of network processor is generally called a run-to-complete (English: run to complete) architecture. Among them, the characteristic of the first type of network processor is that after re...

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Problems solved by technology

[0005] During the research and practice of the prior art, the inventor found that the main problem of using the parallel pipeline architecture in the prior art is that the resources it consumes (such as table lookup bandwidth, instruction bandwidth, power consumption, etc.) increase with the parallel pipeline. increase proportionally

However, the speed of semiconductor process improvement is far behind the speed of network equipment bandwidth demand growth. Therefore, providing these resources is a great challenge for chip implementation.

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