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SiC grooved metal oxide semiconductor field effect transistor (MOSFET) with integration of Schottky diode and fabrication method of SiC grooved MOSFET

A Schottky diode and trench type technology, which is applied in semiconductor/solid-state device manufacturing, diodes, semiconductor devices, etc., can solve problems that affect device reliability, increase device manufacturing costs, increase circuit power consumption, etc., and improve efficiency and reliability, reducing material and process costs, and avoiding the effect of increasing BPD dislocations

Pending Publication Date: 2016-06-01
GLOBAL ENERGY INTERCONNECTION RES INST CO LTD +2
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Although the SiC-based MOSFET also has a naturally formed anti-parallel diode, due to the high band gap of SiC, the turn-on voltage of the PN junction diode is high, reaching about 3V. When using the anti-parallel diode inside the SiC MOSFET, the circuit will be greatly increased. At the same time, since the base sagittal plane dislocation in SiC material will induce stacking fault due to the work of PN junction, the use of its internal PN junction diode as anti-parallel diode will affect the reliability of the device
When using SiC MOSFET devices, it is generally necessary to connect SiC Schottky diodes in anti-parallel externally, but this will increase the manufacturing cost of the devices

Method used

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  • SiC grooved metal oxide semiconductor field effect transistor (MOSFET) with integration of Schottky diode and fabrication method of SiC grooved MOSFET
  • SiC grooved metal oxide semiconductor field effect transistor (MOSFET) with integration of Schottky diode and fabrication method of SiC grooved MOSFET
  • SiC grooved metal oxide semiconductor field effect transistor (MOSFET) with integration of Schottky diode and fabrication method of SiC grooved MOSFET

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0049] First, the N-drift layer is epitaxially grown on the N+ substrate, the thickness of the drift layer is 12 μm, and the doping concentration is 2×10 15 cm -3 . The resistivity of the N+ substrate is 0.015-0.02 ohm-cm.

[0050] Then, the pattern to be doped is etched on the mask plate on the N-drift layer, and the ion implantation process of the P wells is performed. The distance between the P wells is 1 μm, and the depth of the P wells is 1 μm. This part is used to form a Schottky contact with the metal.

[0051] Next, the pattern of the N+ source region is etched using a mask, and the ion implantation process of the N+ source region is performed. The depth of the N+ source region is smaller than the P well, which is 0.5 μm, and the width is also smaller than the P well.

[0052] Next, the pattern of the gate groove (U-shaped channel) was etched using a mask, and the groove was formed by reactive ion etching (RIE) or inductively coupled plasma etching (ICP), with a dep...

Embodiment 2

[0060] First, the N-drift layer is epitaxially grown on the N+ substrate, and the thickness of the drift layer is 15 μm. The doping concentration is 1×10 15 cm -3 . The resistivity of the N+ substrate is 0.015-0.02 ohm-cm.

[0061] Then, the pattern to be doped is etched on the mask plate on the N-drift layer, and the ion implantation process of the P wells is performed. The distance between the P wells is 1.5 μm, and the depth of the P wells is 1 μm. This part is used to form a Schottky contact with the metal.

[0062] Next, the pattern of the N+ source region is etched using a mask, and the ion implantation process of the N+ source region is performed. The depth of the N+ source region is smaller than the P well, which is 0.5 μm, and the width is also smaller than the P well.

[0063] Next, a gate groove (U-shaped channel) pattern was photoetched using a mask, and a groove was formed by reactive ion etching (RIE) or inductively coupled plasma etching (ICP) with a depth of...

Embodiment 3

[0071] First, the N-drift layer is epitaxially grown on the N+ substrate, the thickness of the drift layer is 50 μm, and the doping concentration is 8×10 14 cm -3 . The resistivity of the N+ substrate is 0.015-0.02 ohm-cm.

[0072] Then, the pattern to be doped is etched on the mask plate on the N-drift layer, and the ion implantation process of the P wells is performed. The distance between the P wells is 1.5 μm, and the depth of the P wells is 1.5 μm. This part is used to form a Schottky contact with the metal.

[0073] Next, the pattern of the N+ source region is etched using a mask, and the ion implantation process of the N+ source region is performed. The depth of the N+ source region is smaller than the P well, which is 0.5 μm, and the width is also smaller than the P well.

[0074] Next, a gate groove (U-shaped channel) pattern was photoetched using a mask, and a groove was formed by reactive ion etching (RIE) or inductively coupled plasma etching (ICP), with a depth...

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Abstract

The invention provides a SiC grooved metal oxide semiconductor field effect transistor (MOSFET) with integration of a Schottky diode and a fabrication method of the SiC grooved MOSFET. The transistor comprises: 1) a grooved MOSFET comprising an N+ substrate and an N- drift layer on the N+ substrate, wherein the N- drift layer comprises P wells, U-shaped channels outside the P wells, a gate, an isolation layer on parts of N+ source regions, a source on the front surface and a drain on the back surface, the P wells are provided with the N+ source regions and are isolated, oxide layers are arranged on the surface of the U-shaped channels, and the gate is arranged in the U-shaped channels; and 2) the Schottky diode, in which the N- drift layer among the P wells in the N- drift layer forms Schottky contact with source metal. By introducing the Schottky diode into the grooved SiC MOSFET, an effect of a fly-wheel diode is developed during device working, the working efficiency and reliability of a circuit are improved, and the fabrication cost of the circuit is reduced.

Description

technical field [0001] The invention relates to a semiconductor device, in particular to a SiC trench type MOSFET device integrating a Schottky diode and a manufacturing method thereof. Background technique [0002] Silicon carbide (SiC) is the third-generation semiconductor material developed after the first-generation semiconductor materials silicon, germanium and the second-band semiconductor materials gallium arsenide and indium phosphide. The wide bandgap of silicon carbide materials is silicon and arsenide 2 to 3 times that of gallium, so that semiconductor devices can work at a relatively high temperature (above 500 ° C) and have the ability to emit blue light; its high breakdown electric field is an order of magnitude higher than that of silicon and gallium arsenide, which determines the semiconductor The high-voltage and high-power performance of the device; its high saturated electron drift velocity and low dielectric constant determine the high-frequency and high-...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/04
CPCH01L21/0445H01L29/66068H01L29/7806H01L21/04H01L29/78
Inventor 钮应喜郑柳杨霏温家良潘艳李永平王嘉铭李玲夏经华朱韫晖
Owner GLOBAL ENERGY INTERCONNECTION RES INST CO LTD