Semiconductor device forming method

Abstract

The invention discloses a semiconductor device forming method, and the method comprises the steps: providing a substrate with a first region and a second region, wherein the surface of the substrate is provided with a first dielectric layer and the surface of the first region of the substrate is provided with a conductive plug; forming a second dielectric layer on the surface of the first dielectric layer, wherein the interior of the second dielectric layer is provided with a plurality of first openings; exposing the top of the conductive plug at the bottom of the first opening in the first region; forming a first conductive layer in the first opening; then carrying out the etching of the second dielectric layer and the first dielectric layer of the second region till the substrate is exposed, so as to form a second opening; forming a passivation region in the substrate at the bottom of the second opening; exposing the surface of the first dielectric layer of the second region; forming third dielectric layers in the second opening and on the surface of the first dielectric layer, wherein the surfaces of the third dielectric layers are aligned with the surfaces of the second dielectric layer and the first dielectric layer located in the first region; and forming third conductive layer on the surfaces of the third dielectric layers. The method improves the performance of a formed semiconductor device, and simplifies the forming steps.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor device. Background technique [0002] In an existing integrated circuit, such as a radio frequency front-end module (RFFEM), an inductor is an important electrical device, and its performance parameters directly affect the performance of the integrated circuit. In the prior art, most of the inductors in integrated circuits use planar inductors, such as planar spiral inductors; the planar spiral inductors are formed by winding metal wires on the surface of a substrate or a dielectric layer; compared with traditional wire wound inductors, planar inductors The device has the advantages of low cost, easy integration, low noise and low power consumption, and more importantly, it is compatible with today's integrated circuit technology. [0003] Please refer to figure 1 and figure 2 , is a schematic structural diagram of a pl...

AI Technical Summary

Problems solved by technology

[0006] However, the quality factor Q of existing planar inductors is too low, and the process steps for forming planar inductors are less integrated with the process steps for forming other semiconductor devices, making the process more complicated

Images