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Peripheral component interconnect

A technology for interconnection of peripheral components and bus, applied in digital data processing components, instruments, electrical digital data processing, etc., can solve problems such as lowering communication quality, inconsistent differential impedance, affecting signal integrity and time delay, etc., to improve The effect of communication quality

Inactive Publication Date: 2016-08-10
LETV HLDG BEIJING CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the process of realizing the present invention, the inventor found that there are at least the following problems in the prior art: the design of the current smart TV tends to be flat, which seriously compresses the space of the PCI bus
If the communication circuits of different peripheral interface circuits are combined on the same printed circuit board, since the differential impedance required by different peripheral interface circuits is inconsistent, it will affect the integrity and time delay of the signal, thereby reducing the communication quality.

Method used

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Examples

Experimental program
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Embodiment 1

[0032] Embodiment 1 of the present invention provides a bus for interconnecting peripheral components. figure 1 It is a schematic diagram of the peripheral component interconnection bus provided by Embodiment 1 of the present invention. Such as figure 1 As shown, the peripheral component interconnection bus includes: a printed circuit board surface layer for communicating with a first peripheral interface circuit and a printed circuit board bottom layer for communicating with a second peripheral interface circuit, and the printed circuit board surface layer includes a The contact wires on the surface are proportioned to conform to the differential impedance of the first peripheral interface circuit, and the bottom layer of the printed circuit board includes the bottom contact lines that are proportioned to conform to the differential impedance of the second peripheral interface circuit. Interface multiplexed peripheral component interconnection bus PCI bus can be divided into...

Embodiment 2

[0037] figure 2 It is a schematic diagram of the microscopic shape of a surface contact line in the interconnection bus of peripheral components provided by Embodiment 2 of the present invention; image 3 It is a schematic diagram of the microscopic shape of a bottom contact line in the peripheral component interconnection bus provided by Embodiment 2 of the present invention. This embodiment is based on the above-mentioned embodiments. Specifically, the surface contact line 3 is set as a contact line with a first preset length, and the preset length is determined according to the differential impedance of the first peripheral interface circuit; the bottom contact line 4 The contact line is set as a second preset length, and the second preset length is determined according to the differential impedance of the second peripheral interface circuit. Since the length of the contact wire can affect the differential impedance, the length of the contact wire can be determined throug...

Embodiment 3

[0039] Figure 4 It is a schematic diagram of the surface layer of the printed circuit board in the peripheral component interconnection bus provided by the third embodiment of the present invention; Figure 5 It is a schematic diagram of the bottom layer of the printed circuit board in the peripheral component interconnection bus provided by Embodiment 3 of the present invention. This embodiment is based on the above-mentioned embodiment. Specifically, the surface layer contact line 3 includes: several contact lines arranged at equal intervals, and the distance is determined according to the differential impedance of the first peripheral interface circuit; the bottom layer contact line 4 includes: : several contact wires arranged at equal intervals, the intervals being determined according to the differential impedance of the second peripheral interface circuit. Since the spacing between the contact lines can affect the differential impedance, the spacing between the contact...

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Abstract

The invention discloses a peripheral component interconnect, and belongs to the technical field of communications. The peripheral component interconnect comprises a printed circuit board surface layer for communicating with a first peripheral interface circuit, and a printed circuit board bottom layer for communicating with a second peripheral interface circuit, wherein the printed circuit board surface layer comprises a surface layer contact line which is configured to conform to differential impedance of the first peripheral interface circuit; and the printed circuit board bottom layer comprises a bottom layer contact line which is configured to conform to differential impedance of the second peripheral interface circuit. The surface layer contact line and the bottom layer contact line are configured to conform to the differential impedance of the corresponding interface circuits, so that the problem that different interface circuits have different differential impedance can be solved, and the data transmission accuracy is increased.

Description

technical field [0001] The invention relates to the technical field of communication, in particular to a bus for interconnecting peripheral components. Background technique [0002] Peripheral Component Interconnect (PCI) and PCI-E (PCI Express) are bus structures that combine peripheral devices and processors at a high speed, so as to meet the increasing requirements of users for data rates. Devices using the PCI bus structure can achieve a theoretical peak data rate of 132Mbytes / s. An outstanding advantage of using the PCI bus is that the CPU (Central Processing Unit) occupancy rate is extremely low, and the interaction between it and the memory is basically through DMA, so PCI bus devices can be used for occasions that require high data rates and low consumption. [0003] The existing PCI bus usually consists of a PCI interface chip and a configuration chip. In the process of realizing the present invention, the inventors have found at least the following problems in th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/18G06F13/40
CPCG06F1/183G06F13/4068G06F13/4086G06F1/18
Inventor 常琪
Owner LETV HLDG BEIJING CO LTD