A time-sharing storage circuit structure used in otn packet switching interface chip
A technology of interface chips and storage circuits, which is applied in the fields of electrical digital data processing and instruments, can solve problems such as difficult error control, low utilization rate of network bandwidth, and difficulty in communicating with each other, so as to reduce address delay, reduce complexity, and improve The effect of work rate
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[0018] Such as figure 1 , as shown in 2, this patent designs a time-sharing storage circuit structure used inside the OTN packet switching interface chip, including dividing and storing different types of data in sequence according to time slots, which reduces the complexity of circuit layout and wiring in address selection , improve the speed of circuit operation, and realize high-speed and stable data transmission in a large number of cross-clock domain transmissions. In the packet switching circuit of the OTN chip, ODU0 data is allocated according to the time slot method, so that 8 channels of ODU0 data coming at the same time are stored in a dual-port RAM.
[0019] Firstly, the read enable of the upper-level asynchronous FIFO is generated. In the 8 cutting circuits odu0_seg0 to odu0_seg7, when the port with the cutting circuit is enabled, and when the internal data cache counter is less than 109, the read enable of the upper-level corresponding asynchronous FIFO is generat...
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