Wafer bonding method and chemical mechanical planarization method

Abstract

A wafer bonding method and a chemical mechanical polishing method are disclosed. The wafer bonding method comprises the following steps: providing a device wafer and a carrier wafer; forming a first material layer on the front of the device wafer; planarizing the first material layer using a first chemical mechanical polishing method, wherein the first chemical mechanical polishing method includes a first swinging polishing step and a first fixed polishing step, at least part of a positioning ring in a polishing head is suspended beyond the scope right above a polishing pad in the first fixed polishing step, and the maximum distance from the suspended portion of the positioning ring to the edge of the polishing pad is greater than or equal to the width of the positioning ring; and after the first chemical mechanical polishing method, bonding the device wafer and the carrier wafer together. Through the wafer bonding method, the bonding performance and bonding yield of wafers are improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a wafer bonding method and a chemical mechanical planarization method. Background technique [0002] Please refer to figure 1 , in the chip wafer level packaging (wafer level package, WLP) process, the chip device wafer (device wafer) 100 usually needs to be bonded (bonding) with the carrier wafer (carrier wafer) 200 together, and then Subsequent processes such as wafer thinning and wafer-level packaging are carried out. Especially in the three-dimensional chip (3DIC) structure, the carrier wafer 200 is more commonly used in the wafer-level packaging process of the three-dimensional chip. [0003] However, please refer to figure 2 , in the back-end-of-line (BEOL) of the device wafer 200 , it is usually necessary to form copper interconnection lines on the interlayer dielectric layer 210 . When forming copper interconnect lines, it is necessary to deposit, for examp...

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Problems solved by technology

[0005] However, please refer to image 3 , the existing wafer bonding method cannot well eliminate the height difference between the front edge region of the device wafer 200 and other regions, resulting in that after the device wafer 200 and the carrier wafer 100 are bonded (usually the device wafer 200 is made by The oxide layer 230 on the front side is bonded to the carrier wafer 100), and gaps (void) 12 appear on the edges of their bonding surfaces.

The existence of the gap 12 reduces the bonding yield of the device wafer 200 and the carrier wafer 100

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