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High-speed FPGA boot through parallel multi-frame configuration scheme

A technology of data and line segments, which is applied in the field of high-speed FPGA startup through parallel multi-frame configuration schemes, and can solve problems such as impossibility and long data frame configuration time

Active Publication Date: 2019-10-01
ALTERA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Accordingly, applications that require startup times faster than programming times provided in programmable integrated circuit devices such as FPGA devices cannot be implemented in such devices.
Typically, these bottlenecks are formed because the configuration time is not scalable in conventional programmable integrated circuit devices, and thus, the larger the device required to run the application, the larger the configuration time per data frame becomes

Method used

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  • High-speed FPGA boot through parallel multi-frame configuration scheme
  • High-speed FPGA boot through parallel multi-frame configuration scheme
  • High-speed FPGA boot through parallel multi-frame configuration scheme

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Embodiment Construction

[0014] figure 1 Some embodiments according to the present disclosure describe a programmable integrated circuit device comprising: a configuration source, a data register, a data line segment, and an address register. Programmable integrated circuit device 100 may include configuration source 102 , data register 104 , data line segment 106 , address register 108 , CRAM 110 , and cache line 112 . Configuration source 102 contains data for sending to data store 104 . As shown, the letter "a" corresponds to the amount of time necessary to transfer data from configuration source 102 through data register 104 . Once data register 104 has received data from configuration source 102 , data register 104 propagates the data from data register 104 to each data line segment 106 in order to write the data to each CRAM 110 . As the data travels along the data lines, the buffer column 112 buffers the data again to ensure that the strength of the signal does not deteriorate as the data tra...

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Abstract

This application relates to high-speed FPGA startup through a parallel multi-frame configuration scheme. Provided herein are systems and methods for implementing programmable integrated circuit devices that enable high-speed FPGA boot by significantly reducing configuration time. By enabling high-speed FPGA startup, the programmable integrated circuit device will be able to accommodate applications that require faster startup times than conventional programmable integrated circuit devices can accommodate. To achieve high-speed startup, dedicated address registers are implemented for each data line segment of the data lines, thereby significantly reducing configuration random access memory (CRAM) write times (eg, by at least a factor of two).

Description

Background technique [0001] Integrated circuit devices such as Field Programmable Gate Array (FPGA) devices are known to suffer from bottlenecks that prevent high speed startup by making them less than optimally configured Random Access Memory (CRAM) programming times. Accordingly, applications provided in programmable integrated circuit devices such as FPGA devices that require a startup time faster than a programming time cannot be implemented in such devices. Typically, these bottlenecks are formed because configuration time is not scalable in conventional programmable integrated circuit devices, and thus, the larger the device required to run an application, the larger the configuration time per data frame becomes. For example, when an FPGA design is scaled more, the data and address lines become larger, thus requiring more time to be configured. Contents of the invention [0002] Provided herein are systems and methods for implementing programmable integrated circuit d...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/445
CPCG06F9/44505G11C7/1039H03K19/1776H03K19/17758G11C7/00G11C8/04G06F9/4403
Inventor 陈俊彬杨钧杰陈俪萍
Owner ALTERA CORP