1.5-bit Redundancy Accelerated Successive Approximation Analog-to-Digital Converter Based on Controllable Asymmetric Dynamic Comparator

Abstract

The invention belongs to the technical field of integrated circuit and specifically relates to a 1.5-bit redundancy acceleration successive approximation analog-to-digital converter (SAR ADC) based on controllable dynamic comparators. The SAR ADC comprises two same gate voltage bootstrap switches, a group of symmetric N-bit binary capacitor array, two controllable dynamic comparators, a common dynamic comparator, and a digital logic circuit module of the SAR ADC. The SAR ADC employs 1.5-bit redundancy acceleration technology, shortens time to wait for the complete establishment of front bits, increases the conversion speed of the ADC, increases redundancy, decreases error codes and lost codes, and increases precision. Compared with the prior art, the SAR ADC may greatly decrease a circuit scale, especially eliminates a reference voltage generation circuit so as to be decreased in power consumption and area, rapidly establishes an equivalent reference voltage value, is increased in conversion speed, has universality, and can be used in other 0.5-bit application cases.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a 1.5-bit redundant accelerated successive approximation digital-to-analog converter based on a controllable asymmetric dynamic comparator. Background technique [0002] The 1.5-bit technology is widely used in pipelined analog-to-digital converters, and the accuracy of the analog-to-digital converters caused by small-magnitude static offset errors is eliminated by increasing redundancy. The first application of 1.5-bit technology in successive approximation analog-to-digital converters was first published by Chun-Cheng Liu and Soon-Jyh Chang at the Symposium on VLSI circuits in 2010, although there was no The concept of 1.5 bits is proposed, but the redundant method implemented therein is indeed a 1.5-bit approach. figure 1 Shown is a schematic diagram of the structure of a 10MS / s, 10bit top plate sampling successive approximation analog-to-digital conve...

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Problems solved by technology

With the development of the technology, the linearity of the metal line is better. The unit capacitance value constructed under the 65nm C MOS process is basically 1fF, which means that the total capacitance value of the capacitor array with the same number of digits is reduced to one-fifth. The flat settling time is greatly shortened, so four 1.5-bit ten-bit successive approximation comparators are used, and the hardware consumption and delay are greater

This design uses a six-bit digital-to-analog converter 108 to generate the reference voltage, which not only consumes a certain area and power consumption, but also easily interferes with the establishment of the level on the capacitor array 102 of the successive approximation comparator, and may introduce an offset. The situation has a greater impact

This also limits the rate of the successive approximation comparator in this structure

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