Phase-locked loop clock jitter simulation method and system

Abstract

The invention provides a phase-locked loop clock jitter simulation method and system which are applicable to embed noise information corresponding to each module in a phase-locked loop into a voltage domain behavioral model so as to acquire a time jitter signal of the phase-locked loop. The method comprises the steps of S1, processing each module in the phase-locked loop by adopting periodic steady state analysis and periodic noise analysis so as to acquire a clock jitter signal of each module; S2, constructing a behavioral model of the phase-locked loop by using a Verilog-A language, and carrying out simulation on the clock jitter signal embedded into each module; S3, when the phase-locked loop of the behavioral model is locked, recording cycle length information of an output waveform of the phase-locked loop in preset time; and S4, calculating an average value and a standard deviation of the cycle length information so as to obtain a clock jitter signal of the behavioral model phase-locked loop and a power spectrum density of a phase. According to the phase-locked loop clock jitter simulation method and system provided by the invention, efficiency of simulating a clock jitter of the phase-locked loop is improved.

Description

technical field [0001] The invention relates to the field of simulation technology, in particular to a simulation method and system for clock jitter of a phase-locked loop. When it is applied to the design of an integrated circuit chip, the noise performance of the phase-locked loop circuit can be monitored in the simulation stage of the circuit principle diagram. predict. Background technique [0002] When the phase-locked loop loop has a steady state, the noise performance of the phase-locked loop is predicted by using the simulation tool SpectreRF. The process of noise analysis includes: using the simulation tool SpectreRF's PSS (Zhousi Steady-State Analysis) to obtain the static operating point in the steady state; when the phase-locked loop does not have a steady state, the analysis results obtained by performing PSS show that it cannot converge, that is, the clock data Restoration circuit, fractional phase-locked loop, and phase-locked loop of any phase detector with ...

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Problems solved by technology

[0006] In view of the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide a simulation method and system of phase-locked loop clock jitter, which is used to solve the clock jitter simulation speed of the phase-locked loop based on the frequency-domain behavior level model in the prior art. too slow problem

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