Method of forming interconnect structure

Abstract

Provided is an interconnection structure forming method, which comprises the following steps: providing a substrate, a front-layer member to be connected being formed in the substrate; forming a patterned first photoresist layer on the substrate; carrying out hardening treatment on the first photoresist layer; forming a filling layer on the first photoresist layer; forming a patterned second photoresist layer on the filling layer; with the second photoresist layer being as a mask, forming a third opening exposing the first photoresist layer; transferring the pattern of the third opening into the substrate, and forming a fourth opening exposing the front-layer member to be connected; and filling a conductive material in the fourth opening to form an interconnection structure. By fixing the pattern of the first photoresist layer for defining the position of a contact hole, definition of the position of the contact hole in a smaller size is allowed to be antecedent to that of the position of a back-layer member to be connected in a larger size, thereby preventing superposition of overlay shift of the two photoetching, expanding contact hole etching process window, improving qualified rate of the device in the manufacturing process and reducing device manufacture cost.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming an interconnection structure. Background technique [0002] With the development of integrated circuits to ultra-large scale integrated circuits, the circuit density inside integrated circuits is getting larger and larger. This development has made it impossible to provide enough area on the wafer surface to make the connecting wires. In order to meet the interconnection requirements of the reduced components, the design of two or more layers of multi-layer metal interconnection lines has become one of the methods commonly used in VLSI technology. At present, conduction between different metal layers or between a metal layer and a liner layer is realized through an interconnection structure. [0003] refer to Figure 1 to Figure 5 , which shows a schematic diagram of a method for forming an interconnection structure in the prior art. Here, the in...

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Problems solved by technology

[0010] However, semiconductor devices formed using the prior art are prone to short circuits between the plug va and the adjacent device mb

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