Semiconductor package assembly and method for forming the same

Abstract

A semiconductor package assembly and a method for forming the same are provided. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The semiconductor package assembly also includes a second semiconductor package bonded to the first semiconductor package. The second semiconductor package includes a second semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. A second RDL structure is coupled to the second semiconductor die. The first RDL structure is positioned between the first semiconductor die and the second RDL structure. Via the semiconductor package assembly and the method for forming the same, designing flexibility can be improved.

Description

【Technical field】 [0001] The present invention relates to a semiconductor package assembly, in particular to a three-dimensional (3D) semiconductor package assembly and a manufacturing method thereof. 【Background technique】 [0002] In order to meet the miniaturization and multi-functional requirements of electronic products, the semiconductor industry has experienced continuous and rapid growth. The integration density has been increased so that more die or chips can be integrated in a semiconductor package, such as a two-dimensional (2D) semiconductor package. However, two-dimensional semiconductor packaging has physical limitations, such as when more than two chips with various functions are placed in a two-dimensional semiconductor device, it becomes difficult to develop the necessary more complex designs and layouts. [0003] Although three-dimensional (3D) integrated circuits and stacked chips have been developed and widely used, the chips integrated in conventional t...

AI Technical Summary

Problems solved by technology

However, two-dimensional semiconductor packaging has physical limitations, such as when more than two chips with various functions are placed in a two-dimensional semiconductor device, it becomes difficult to develop the necessary more complex designs and layouts

[0003] Although three-dimensional (3D) integrated circuits and stacked chips have been developed and widely used, the chips integrated in conventional three-dimensional semiconductor packages are limited to the same size

Furthermore, 3D semiconductor packaging technology also encounters various problems that may lead to a decrease in manufacturing yield

Images