A Hybrid Phase-Locked Loop

Abstract

The invention provides a hybrid phase locked loop and a phase locked loop frequency locking method. The hybrid phase locked loop comprises a clock generator, a phase frequency detector, an analog comparer, a voltage-controlled oscillator, a frequency divider, an analog / digital converter, a microcontroller, a digital / analog converter and loop filter circuit, a fixed gain amplifier and level regulation circuit and a programmable gain amplifier circuit. According to the hybrid phase locked loop and the phase locked loop frequency locking method, through combination of partial advantages of a full digital phase locked loop and an analog phase locked loop, the losing lock problem of the phase locked loop is solved. According to the phase locked loop of the structure, the phase locked loop can enter a locking state whatever working frequency condition the voltage-controlled oscillator VCO is located. The phase locked loop based on the structure is simple in structure and is easy to realize.

Description

technical field [0001] The invention relates to the technical field of phase-locked loops, in particular to a hybrid phase-locked loop. Background technique [0002] Phase-locked loop (PLL) technology is used in many fields, such as the function of frequency synthesis in the field of instrumentation. The implementation of phase-locked loops is usually divided into two ways: all-digital phase-locked loops (ADPLLs) and analog phase-locked loops. The all-digital phase-locked loop includes a time-to-digital converter (TDC), a numerically controlled oscillator (DCO), a digital loop filter (DLF) and other components. The all-digital phase-locked loop converts the time difference of two edges into a digital signal to control the digitally controlled oscillator (DCO). The all-digital phase-locked loop is easily affected by digital clock jitter. The analog phase-locked loop is composed of a voltage-controlled oscillator, a fractional frequency divider, a loop filter, and a charge p...

AI Technical Summary

Problems solved by technology

Analog PLLs are easier to debug than digital PLLs but are susceptible to non-ideal characteristics of analog devices, power supplies, and ambient temperature changes

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