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A clock signal testing method and device

A technology of clock signal and test method, applied in the field of electronic information, can solve the problem of abnormally complex clock tree inspection, and achieve the effect of efficient test

Active Publication Date: 2021-03-19
BEIJING WINNER MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For a digital chip with a large circuit scale, the number of clock signals may be many. For a digital circuit with one million gates, it is not uncommon to have more than 10 clock signals, and each clock signal may exist or More or less enabling control logic and parameter configuration relationship, it is extremely complicated to check such a clock tree with a large number of clocks and high complexity

Method used

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  • A clock signal testing method and device
  • A clock signal testing method and device
  • A clock signal testing method and device

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0052] figure 1 A flow chart showing a clock signal testing method provided by an embodiment of the present invention, such as figure 1 As shown, the method includes:

[0053] Step S1, extracting information related to the clock in the input file through the Perl script, and the input file includes an Excel format file.

[0054] All input clock parameters in the input file (except the workgroup name and the column name) can satisfy the syntax rules of the programming language Verilog. The defined workgroup names and column names are fixed and cannot be modified, while other information such as column names that are not defined may not be extracted by the script. The main content of the input file for the clock signal automation test consists of two parts:

[0055] The first part is the sampling clock (master clock). The sampling clock is used to determine the detection point in time at which the default state of the clock under test is checked. The selection of the sampli...

Embodiment 2

[0088] Figure 4 A schematic diagram showing the structure of the clock signal testing device provided by the embodiment of the present invention, such as Figure 4 As shown, the device 10 includes: a processing module 110 , an output module 120 and a detection module 130 .

[0089]The processing module 110 is used to extract information related to the clock in the input file through the Perl script, and the input file includes an Excel format file;

[0090] An output module 120, configured to generate an output file according to the clock-related information, the file comprising a Verilog file;

[0091] The detection module 130 is configured to call the output file to detect the state of the clock signal in real time, and the state of the clock signal includes the cycle of the clock signal and the duty cycle of the current cycle, or a default state.

[0092] In a possible implementation manner, the detection module 110 is configured to subtract t2_21 from the current rising...

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Abstract

The invention relates to a test method and device of a clock signal. Through a Perl script, information associated with a clock in an input file is extracted, wherein the input file comprises an Excel format file; according to the information associated with the clock, an output file is generated, wherein the file comprises a Verilog file; and the output file is called to detect the state of the clock signal in real time, wherein the state of the clock signal comprises the period of the clock signal and the duty cycle or the default state of the current period. The clock signal can be automatically and efficiently tested.

Description

technical field [0001] The invention relates to the technical field of electronic information, in particular to a clock signal testing method and device. Background technique [0002] As the scale of digital chips increases and the degree of integration increases, the workload of verification work in chip projects also increases. According to industry statistics, chip verification workload accounts for about 70% of the entire chip project development cycle, and improving verification efficiency is the only way to shorten the project development cycle. [0003] Research shows that verification automation and verification module standardization have become an important technical direction in the field of chip verification. Verification automation solves the same and repetitive detection problem for a large number of verification objects, effectively helping verification engineers avoid a lot of simple and repetitive labor, and saving time in the verification process. [0004...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/22
CPCG06F11/2205G06F11/2273
Inventor 梅张雄郭涛
Owner BEIJING WINNER MICROELECTRONICS