Monitorable information processing system
An information processing system and power monitoring technology, applied in electrical digital data processing, climate sustainability, thermometers based on physical/chemical changes, etc., can solve problems such as high power consumption, achieve low power consumption and strong information processing capabilities , the effect of enhancing the reading ability
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Embodiment 1
[0025] Such as figure 1 and figure 2 As shown, a monitorable information processing system includes an FPGA, which is provided with a temperature module for monitoring the core temperature of the FPGA. The FPGA is plugged with 4 CPUs, and the CPU model is MPC8640D, each A temperature sensor chip ADT7461 is attached to the CPU, which is used to monitor the core temperature of the CPU and the temperature of the nearby boards, and output the temperature monitoring results to the FPGA. The FPGA also has a power monitoring chip, which is used to monitor each power supply voltage, and control the power off of the entire board according to the temperature monitoring results output by the FPGA. The monitoring information is transmitted through the I2C bus led out of the FPGA. The CPU described in each chip is connected to the VPX connector through the SRIO bus, PCIE bus and GbE bus. , for data interaction inside and outside the board.
[0026] In the present invention, a piece of F...
Embodiment 2
[0029]This embodiment is a further improvement made on the basis of the above embodiments, such as figure 1 and figure 2 As shown, in this embodiment, the power monitoring chip is ispPAC-POWR1014A of Lattice Company. This chip is powered by 3.3V, and other power sources can be converted to 3.3V through the power conversion chip. This chip has 10 power supply real-time monitoring, 25 Programmable macro unit, 10-way Open-Drain output and I2C interface; the voltage value of any of the 10-way input power sources can be read through the I2C interface, and the overvoltage and undervoltage ratios of the 10-way power supplies can be set, and the internal logic resources can be controlled 10 output signals control the power chip of the whole board.
Embodiment 3
[0031] This embodiment is a further improvement made on the basis of the above embodiments, such as figure 1 As shown, in the present embodiment, the FLASH of 256MB is externally connected to the FPGA, and the FLASH includes two S29GL01GP FLASH chips of Spansion Company, thereby further enhancing the reading capability of information, and the signal lines of the Flash are all connected to FPGA, 4 LocalBus of MPC8640D access Flash through FPGA, and FPGA is also connected with two photoelectric conversion modules, debugging serial port and reset button on the front panel respectively. The 256MB FLASH connected to the FPGA further enhances the ability to read information. The signal lines of the Flash are all connected to the FPGA, and the 4 LocalBus of MPC8640D access the Flash through the FPGA.
[0032] Each CPU is equipped with two DDRs, each of which has a capacity of 512MB. Using 8 pieces of 128MB DDR2 of model MT47H64M16-37E, each group of 4 pieces constitutes 64bit, and e...
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