Method of manufacturing high-threshold-voltage high-mobility grooved gate MOSFET
A high-threshold voltage, high-mobility technology, applied in the manufacture of circuits, electrical components, semiconductors/solid-state devices, etc., can solve problems such as lattice damage in the channel region, lower threshold voltage, and low field-effect mobility, and achieve improved Effect of channel shift, high threshold voltage
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Embodiment 1
[0048] Such as Figure 11 Shown is a schematic diagram of the device structure of this embodiment, and its structure includes a substrate (1), a stress buffer layer (2), a GaN epitaxial layer (3), and a low-aluminum composition AlGaN barrier layer (4) from bottom to top. , a GaN insertion layer (5), a high-aluminum composition AlGaN barrier layer (6), a p-type oxide gate (7), both ends form a source and a drain (8), and an oxide gate (7) Deposit thickening metal (9).
[0049] The fabrication method of the device field effect transistor of the above-mentioned GaN-based groove gate MOSFET is as follows: Figure 1-Figure 11 shown, including the following steps:
[0050] S1. Using the metal organic chemical vapor deposition method, grow a stress buffer layer (2) on the Si substrate (1), such as figure 1 shown;
[0051] S2. Using a metal organic chemical vapor deposition method to grow a GaN epitaxial layer (3) on the stress buffer layer (2), such as figure 2 shown;
[0052] ...
Embodiment 2
[0063] Such as Figure 12 Shown is a schematic diagram of the device structure of this embodiment, which differs from the structure of Embodiment 1 only in that the gate in Embodiment 1 is a single oxide, while in Embodiment 2 two or more oxides are used to form a stacked gate. electrode structure.
Embodiment 3
[0065] Such as Figure 13 Shown is a schematic diagram of the device structure of this embodiment, which differs from the structure of embodiment 1 only in that the gate in embodiment 1 is a p-type oxide, while embodiment 3 introduces an insulating dielectric layer under the p-type oxide gate electrode ( 11), the dielectric layer is Al 2 o 3 or HfO 2 , with a thickness of 1-100 nm; forming a dielectric layer / oxide stack structure.
[0066] In addition, it should be noted that the drawings of the above embodiments are only for illustrative purposes, and thus are not necessarily drawn to scale.
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