Method for improving grid corner at boundary of active area

Abstract

The invention provides a method for improving the grid corner at the boundary of an active area. The method comprises the following steps: judging whether a corner exists in a joint of a grid area and the active area, judging whether a parallel distance between polycrystalline silicon in a non grid area and the active area is within a set safe range; judging whether the size of the polycrystalline silicon in the non grid area is within a set design rule value range or less than the set design rule value range; selecting a polycrystalline silicon graph in the non grid area as a second graph to be corrected; judging whether a distance from the boundary, away from the grid area, of the second graph to be corrected to a boundary of a graph closest to the boundary is within a set correction space; moving the boundary, away from the grid area, of the second graph to be corrected towards a direction away from the grid area; introducing a correction process for controlling the arc at the edge of the grid area to be outwards inclined to correct a first graph to be corrected or the first graph to be corrected and the second graph to be corrected; and performing simulation verification on the corrected graphs.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for improving the gate corner at the boundary of an active region. Background technique [0002] With the shrinking of the size of semiconductor devices, the requirements for the existing process are getting higher and higher, and the requirements for the consistency of key dimensions are becoming more and more stringent, especially to ensure the size consistency of the gate oxide layer and the gate layer. The size of the gate oxide layer is determined by the size of the cross-sectional area of ​​the gate, which will affect the amount of current passing through the gate, and ultimately affect the control of the gate on the channel. There must be a certain error range in the process from designing graphics to actual imaging, such as figure 1 As shown, the dotted line box shown in G' is the gate area, P' is polysilicon, A' is the active area, and the corners caused...

AI Technical Summary

Problems solved by technology

The size of the gate oxide layer is determined by the cross-sectional area of ​​the gate, which affects the amount of current passing through the gate, and ultimately affects the control of the gate to the channel.

There must be a certain error range in the process from designing graphics to actual imaging, such as figure 1 As shown, the dotted line box shown in G' is the gate area, P' is polysilicon, A' is the active area, and the corners caused by optical effects become rounded, as shown in figure 1 As shown in a, the gate area at this location is larger than the surface of the target gate, that is, the actual imaging area of ​​the gate is larger than the area required by the design, resulting in an increase in the area of ​​the gate oxide layer at this location

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